EPC2LI20J - 1.6Mb ISP Config PROM 20-PLCC | Altera
MPN: EPC2LI20J ✓ نشطEPC2LI20J نظرة عامة
An FPGA configuration PROM is a non-volatile serial flash device that stores the FPGA's bitstream and presents it to the FPGA at power-up via a serial configuration protocol, replacing parallel EEPROMs and reducing board area and pin count. The EPC2 family sits in the broader taxonomy: configuration PROM -> non-volatile memory -> serial flash -> semiconductor memory. It is a companion device rather than a general-purpose memory and is only ever used as part of an Altera FPGA boot circuit.
Key features of the EPC2LI20J include 1.6Mb flash storage with 8-bit data width internally serialized through the Altera serial configuration interface, ISP programmability via JTAG, multi-device cascade support for configuring multiple FPGAs from a single chain, and a built-in oscillator that eliminates the need for an external configuration clock. The device is supported by the legacy Altera Quartus II programmer (PS mode) and remains in production for long-life industrial and military programs that maintain APEX/FLEX/Mercury designs.
Typical applications include APEX II, APEX 20K, ACEX 1K, FLEX 6000, FLEX 10KE and Mercury FPGA configuration memory, factory-floor industrial controllers using FLEX 10KA, and military/aerospace programs with long-life FPGA designs. The PLCC-20 through-hole/socketed form factor suits designs where field reprogrammability or in-system recovery is required.
When designing with the EPC2LI20J, follow Altera's reference schematic: route MSEL pins on the target FPGA to FPP/PS mode, connect nCONFIG/nSTATUS between PROM and FPGA, and ensure the JTAG chain order matches the Quartus programmer file. A 0.1uF decoupling capacitor close to VCC is mandatory.
This page consolidates distributor stock, same-brand drop-in alternatives, and configuration-design notes not found in the standalone Altera datasheet.
بدائل مباشرة لـ EPC2LI20J — نفس الحزمة، متوافق دبوس بدبوس. تُستثنى القطع ذات الحزم المختلفة التي تتطلب تعديل PCB.
الطرازات في هذه السلسلة
طرازات من نفس السلسلة متوافقة تمامًا مع EPC2LI20J (نفس عامل الشكل والبصمة) — يختلف في Memory Type, Memory Size, Mounting Type, Package, Configuration Interface.
EPC2LI20
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←EPC2LI20N
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←EPC2LC20
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←EPC2LC20N
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←EPC1LC20
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←EPC2LI20J الحدود القصوى والخصائص الكهربائية
| نوع الذاكرة | In-System Programmable Configuration PROM (flash) |
| حجم الذاكرة | 1,695,680 bits (1.6Mb) |
| التنظيم | 65,536 x 1-bit (serial interface) |
| الواجهة | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) |
| Target FPGAs | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Voltage (VCCIO) | 5.0 V or 3.3 V tolerant |
| ISP Programming Interface | JTAG (IEEE 1149.1) |
| Cascade Support | Yes (multi-device configuration chain) |
| Internal Oscillator | Yes (configures without external clock source) |
| العلبة | 20-pin PLCC with J-leads (JEDEC MS-018) |
| درجة حرارة التشغيل | -40C to +85C (industrial) |
| Configuration Clock (DCLK) | Up to 33 MHz |
تكوين أطراف EPC2LI20J
| دبوس 1 | DATA — Serial configuration data output to FPGA DATA0/DATA1 pin |
| دبوس 2 | DCLK — Configuration clock output (up to 33 MHz) |
| دبوس 3 | nCS — Chip select (active low) for cascade mode |
| دبوس 4 | nCONFIG — Configuration control (active low, open-drain) |
| دبوس 5 | nSTATUS — Configuration status output to FPGA (active low) |
| دبوس 6 | VCC — 3.3V core supply voltage |
| دبوس 7 | GND — Ground reference |
| دبوس 8 | TDI — JTAG Test Data In (IEEE 1149.1) |
| دبوس 9 | TMS — JTAG Test Mode Select |
| دبوس 10 | TCK — JTAG Test Clock |
| دبوس 11 | nCE — Chip Enable (active low, cascade mode) |
| دبوس 12 | nCASC — Cascade output (active low) for multi-PROM chain |
| دبوس 13 | OE — Output Enable (active low) |
| دبوس 14 | nINIT_CONF — Initiate configuration (active low) |
| دبوس 15 | PWRDWN — Power-down input (unused, tie high) |
| دبوس 16 | TDO — JTAG Test Data Out |
| دبوس 17 | VCCIO — I/O supply (3.3V or 5V tolerant) |
| دبوس 18 | CFG_DONE — Configuration complete flag |
| دبوس 19 | CONF_DONE — Configuration done indicator (open-drain) |
| دبوس 20 | RSV — Reserved - leave floating or tie to GND per datasheet |
التطبيقات النموذجية
EPC2LI20J مناسب لـ 6 التطبيقs: APEX 20K FPGA Configuration Memory, APEX II High-Density FPGA Boot, Mercury FPGA Configuration (EP1M Series), ACEX 1K FPGA Configuration, FLEX 10KE / 10KA / 6000 Configuration, Industrial PLC / Factory Automation Controllers.
APEX 20K FPGA Configuration Memory
The EPC2LI20J is the reference configuration PROM for Altera APEX 20K, 20KC, and 20KE family FPGAs, providing 1.6Mb of flash to hold the full configuration bitstream. At power-up the PROM serially shifts the bitstream to the FPGA via the 4-pin Altera configuration interface (DATA, DCLK, nCS, nCONFIG) at DCLK rates up to 33 MHz, completing configuration of an EP20K400 in roughly 25 ms. The 1.6Mb ceiling matches the largest APEX 20K bitstreams, eliminating the need for two cascaded PROMs. Industrial PLCs, telecom backplane controllers, and military signal-processing boards built around APEX 20K rely on the EPC2LI20J for repeatable in-system reprogramming via JTAG.
موصى به
APEX II High-Density FPGA Boot
The EPC2LI20J supports the largest APEX II devices including EP2A15, EP2A25, EP2A40, and EP2A70, where 1.6Mb of flash is required to hold the bitstream. The PROM's built-in oscillator drives the configuration clock without an external source, simplifying board design and reducing BOM count. Cascade mode allows a single EPC2LI20J to configure two APEX II devices sequentially when one PROM cannot supply enough bandwidth. APEX II designs in military radar, sonar, and ASIC-prototype emulation use the EPC2LI20J for field-recoverable configuration. The PLCC-20 socket form factor suits designs that may need to swap FPGAs or PROMs during board bring-up.
موصى به
Mercury FPGA Configuration (EP1M Series)
Altera Mercury (EP1M) FPGAs are 0.18um SRAM-based devices with embedded transceivers, used in high-speed serial I/O designs. The EPC2LI20J provides 1.6Mb of flash to hold Mercury bitstreams up to EP1M350 density, with cascade support for multi-FPGA Mercury boards. The PROM's 3.3V VCCINT and 5V-tolerant I/O match Mercury's mixed-voltage I/O requirements. The PLCC-20 footprint is preferred for prototype boards where engineers may socket the PROM for development testing. Mercury reference designs in industrial test equipment and high-speed data acquisition use the EPC2LI20J as the primary boot source.
موصى به
ACEX 1K FPGA Configuration
The EPC2LI20J is specified by Altera for configuring ACEX 1K family devices including EP1K10, EP1K30, EP1K50, and EP1K100. Because ACEX 1K bitstreams rarely exceed 1Mb, the EPC2LI20J provides 60% headroom for design iteration without re-programming or re-sourcing the PROM. JTAG ISP allows field updates via standard IEEE 1149.1 boundary-scan chains, eliminating the need for a parallel programmer. The PLCC-20 socket form factor suits low-volume ACEX 1K designs in instrumentation and prototyping. The EPC2LI20J's industrial -40C to +85C temperature range covers most ACEX 1K applications including factory automation and outdoor telecom gear.
موصى به
FLEX 10KE / 10KA / 6000 Configuration
Older FLEX 10KE, FLEX 10KA, and FLEX 6000 family FPGAs continue to be deployed in long-life industrial, medical, and aerospace programs. The EPC2LI20J serves as the modern configuration source for these legacy FPGAs, replacing obsolete EPC1 or third-party PROMs with a still-supported Altera-qualified part. Multi-FPGA FLEX boards benefit from EPC2LI20J cascade mode, which strings multiple PROMs to load several FPGAs in sequence. The PLCC-20 socket supports field upgrades in installed equipment. FLEX 6000 designs in medical imaging and process control rely on the EPC2LI20J for non-volatile bitstream retention over 10+ year deployment horizons.
موصى به
Industrial PLC / Factory Automation Controllers
Factory automation controllers built on APEX 20K, ACEX 1K, or FLEX 10KE FPGAs use the EPC2LI20J as the boot PROM because of its industrial -40C to +85C temperature range and PLCC-20 socket form factor for field replacement. The PROM's JTAG ISP interface supports remote firmware updates over the factory's JTAG-extender network, enabling rapid configuration rollouts without physical PROM swap. The 1.6Mb flash ceiling accommodates firmware plus customer-specific IP cores plus soft-core Nios processors, all stored in unused PROM memory as documented in the Altera datasheet. PLC and motor-control applications particularly benefit from cascade mode, where one PROM boots the FPGA and a co-processor FPGA in the same chassis.
موصى به
ملخص المنتجات الموصى بها
بيانات مرجعية هندسية لـ EPC2LI20J — المقارنة وإرشادات التصميم ومعلومات الامتثال.
دليل الاختيار
المقارنة مع البدائل
| المعامل | هذا المنتج | EPC2LI20 | EPC2LI20N | EPC2LC20 | EPC2LC20N | EPC1LC20 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 20-PLCC J-lead (9x9) | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same | 20-PLCC (9x9) - same |
| Density | 1.6Mb (1,695,680 bits) | 1.6Mb | 1.6Mb | 1.6Mb | 1.6Mb | 1Mb (-37.5%) |
| Configuration Interface | Altera 4-pin serial (DATA/DCLK/nCS/nCONFIG) | Same 4-pin serial | Same 4-pin serial | Same 4-pin serial | Same 4-pin serial | Same 4-pin serial, older |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | No (parallel mode only) |
| Internal Oscillator | Yes | Yes | Yes | Yes | Yes | No |
| Cascade Mode | Yes (multi-FPGA chain) | Yes | Yes | Yes | Yes | Limited |
| Lead Style | J-lead | Gull-wing | Gull-wing, lead-free | Gull-wing | Gull-wing, lead-free | Gull-wing |
أبرز الفروقات
- Highest-density 1.6Mb configuration PROM in 20-pin PLCC (مقابلEPC1LC20)
- J-lead package variant for socketed legacy designs (مقابلEPC2LI20)
- Built-in configuration oscillator eliminates external clock (مقابلEPC1LC20)
ملاحظات التصميم
Mount a 0.1uF X7R decoupling capacitor within 3 mm of pin 6 (VCC) and a 10uF bulk tantalum or aluminum polymer capacitor near pin 17 (VCCIO). Both supply rails must rise together within Altera's specified power-on ramp; if VCCIO leads VCCINT by more than a few hundred milliseconds the PROM may latch in an undefined state. Tie pin 20 (RSV) to GND through a 10k resistor per Altera reference schematic to suppress noise on the reserved input.
Route DATA (pin 1) and DCLK (pin 2) as a 50-ohm microstrip pair to the FPGA's DATA0 and DCLK pins; keep trace length under 50 mm to avoid ringing above the 33 MHz DCLK edge rate. Place the EPC2LI20J within 100 mm of the FPGA so the nCONFIG/nSTATUS open-drain hand-shake signals do not pick up crosstalk. In cascade mode, route nCASC (pin 12) from one PROM to nCS (pin 3) of the next PROM with a 22-ohm series terminator.
Do not connect the EPC2LI20J to FPGAs outside the supported family list (APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA). Modern Stratix, Cyclone, Arria, and Agilex devices require EPCQ or EPCQ-A configuration PROMs with different pinouts and protocols - cross-use will fail silently. Also verify the FPGA's MSEL pins are strapped for PS (passive serial) mode, not FPP or AS mode, because EPC2 devices only support PS configuration.
معلومات الامتثال
Compliance status not stated in the verified web data; consult Altera/Intel FPGA product page or PCN documents for definitive RoHS/REACH status. This part is a legacy configuration PROM with mature process node; many variants were originally released as SnPb-lead finish before RoHS mandates.
