ADC/DAC
Products (2518)
ADC12030CIWM - 12-Bit+Sign SAR ADC, 2-Ch MUX | Texas Instruments
The Texas Instruments ADC12030CIWM is a self-calibrating 12-bit-plus-sign serial I/O analog-to-digital converter with an integrated 2-channel analog input multiplexer and sample-and-hold, packaged in a 16-pin SOIC Wide. According to the Texas Instruments datasheet, it provides up to 114 ksps sampling rate on either 1 or 2 single-ended/differential input channels, uses an external reference, and exposes a 4-wire SPI/QSPI/MICROWIRE-compatible serial interface. Built on a CMOS process with a successive-approximation register (SAR) architecture, it includes on-chip self-calibration that corrects offset and linearity errors, eliminating the need for user trim. A successive-approximation ADC (SAR ADC) is a type of analog-to-digital converter that performs a binary search across the reference range using an internal sample-and-hold, a comparator, a DAC, and a successive-approximation register. SAR ADCs are valued for deterministic latency, no pipeline delay, low power dissipation, and excellent DC accuracy. They sit within the broader hierarchy of ADC architectures (SAR -> Nyquist-rate ADC -> data converter -> signal-chain IC -> semiconductor), and are typically paired with op-amps, voltage references, and MCU SPI peripherals to form complete analog front-ends. Key features include 12-bit resolution plus sign extension (effective 13-bit dynamic range for measurements crossing zero), a self-calibration command for on-demand linearity correction, an external voltage reference (typically 5 V) for ratiometric or absolute measurements, a wide common-mode input range when used in differential mode, and an SPI/QSPI/MICROWIRE-compatible serial data interface. Operating from a single +5 V analog supply and a +5 V (or +3.3 V logic-compatible) digital supply, the device draws only a few milliwatts during continuous conversion and reduces to nanoamp-level standby when CS is held high. Typical applications include precision industrial process control, portable data-logging instruments, automotive sensor signal conditioning (where single-supply operation and wide input range are critical), battery-powered handheld multimeters, and closed-loop position/speed control in motor drives. The on-chip MUX and sample-hold enable direct connection to bridge sensors, thermocouples via front-end amplification, and potentiometric transducers, while the serial interface simplifies isolated data acquisition. When designing with the ADC12030CIWM, ensure the analog and digital grounds are joined only at one star-point beneath the ADC ground pin to avoid digital-noise coupling into the reference. Use a 0.1 uF ceramic bypass capacitor directly on AV+ and a 10 uF tantalum/ceramic bulk capacitor nearby. The reference voltage should be driven from a low-noise, low-drift source such as the TI REF5040 or REF02. This page synthesizes distributor pricing, drop-in alternative MPNs from the same ADC12030 family, and practical PCB layout notes not collected in a single document elsewhere - an at-a-glance decision aid for engineers evaluating the ADC12030CIWM for new designs or as a replacement in legacy boards.
ADC12030CIWMX/NOPB - 12-Bit+Sign SAR ADC, 2-Ch MUX, 16-SOIC | TI
The Texas Instruments ADC12030CIWMX/NOPB is a self-calibrating 12-bit plus sign serial I/O successive-approximation analog-to-digital converter with an integrated 2-channel analog multiplexer and sample/hold amplifier, housed in a 16-pin SOIC (Wide, 7.50mm) package. It supports a single +5V analog supply, samples at up to 114 kS/s, and provides both unipolar (0 to 5V) and bipolar (±5V, ±10V, 0 to 10V) input ranges via pin strapping. An SAR (successive-approximation-register) ADC is a sampling converter that resolves an analog input to a digital code in N clock cycles by iteratively testing each bit with an internal DAC, then holding the result in the sample/hold. SAR ADCs are valued in industrial and instrumentation channels for their deterministic latency, lack of pipeline delay, and excellent behavior on multiplexed inputs where the input settles between conversions. The ADC12030 family sits at the mid-resolution / mid-speed tier of TI's SAR portfolio, above the 8-bit ADC080x family and below 14-/16-bit parts such as the ADS774/ADS780x. Key specifications include 12-bit resolution plus a sign bit for true bipolar operation, 2 single-ended or 1 differential input channel, MICROWIRE-compatible serial interface, on-chip self-calibration that nulls offset and gain errors, low power dissipation of approximately 33 mW at full speed, and an industrial -40C to +85C temperature range. The /NOPB suffix designates a Pb-free (lead-free) finish. The serial data output streams the MSB first across SCLK, framed by an active-low CS, which allows the part to share a 3-wire SPI-like bus with other peripherals and to opto-isolate cleanly in noisy industrial settings. The input MUX is software-selected via two serial bits, so 2-channel scanning is handled without external logic. Typical applications include multi-channel data-acquisition front ends, industrial process control loops, weigh-scale / load-cell signal chains that need true bipolar input range, motor-control feedback boards, and portable instrumentation with handheld sensor interfacing. The 2-channel MUX makes the part economical where only a handful of analog sources must be observed. When designing with this device, add a 0.1 uF ceramic bypass directly on the +5V analog pin and a small RC anti-alias filter on the chosen MUX input. The internal sample/hold requires the input to settle within the acquisition window - source impedance below ~1 kohm is recommended to avoid gain-error and linearity drift. This page synthesizes distributor live pricing, drop-in cross-reference equivalents, and pragmatic design notes derived from the manufacturer datasheet - information not collected together on a single product page elsewhere.
ADC12032CIWM/NOPB - 12-Bit+Sign SAR ADC, 2-Channel | Texas Instruments
The Texas Instruments ADC12032CIWM/NOPB is a 12-bit plus sign, self-calibrating successive-approximation analog-to-digital converter with a 1- or 2-input multiplexer, sample/hold, and serial (MICROWIRE-compatible) I/O, housed in a 20-pin SOIC wide-body (0.295 inch / 7.50 mm) package. The /NOPB suffix confirms Pb-free, RoHS-compliant matte-tin lead finish. The part accepts a single +5 V analog supply, operates up to approximately 5 MHz internal clock (sample rate up to ~73 ksps typical), and provides sign-magnitude output coding ideal for bipolar input ranges. An SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a type of data converter that uses a binary-search algorithm against an internal DAC to digitize an analog input within N clock cycles, where N is the resolution in bits. SAR converters sit in the data-converter hierarchy as: ADC -> SAR ADC -> data converter -> signal chain IC -> semiconductor. They are valued for deterministic latency, single-shot accuracy, and low power consumption, which makes them preferred for multiplexed multi-channel data-acquisition systems rather than continuous high-speed streaming applications. Key features of the ADC12032 include 12-bit resolution with extended-sign coding for ±VREF bipolar inputs, integrated 2-channel analog input multiplexer, on-chip sample-and-hold, self-calibration (offset and gain) registers invoked at power-up or on demand, MICROWIRE/serial-compatible interface for low-pin-count host connection, and a single +5 V supply. The differential non-linearity (DNL) is rated at ±1 LSB maximum, with ±1 LSB integral non-linearity (INL) after calibration. The device uses a charge-redistribution SAR architecture with a binary-weighted capacitor DAC, which inherently provides the sample-and-hold function. The built-in self-calibration trims both zero-scale and full-scale errors against an internal reference node, allowing the part to achieve specified accuracy without external trimming components. The serial data format includes a sign bit, allowing bipolar input ranges without external op-amps. Typical applications include portable and bench-top digital multimeters, weigh scales and load-cell digitizers, panel meters and process-control front ends, temperature/pressure sensor signal chains, and industrial multi-channel data acquisition boards. The internal MUX and self-calibration make it particularly suited for low-channel-count, high-accuracy instrumentation. When designing with this device, place 0.1 µF and 10 µF decoupling capacitors close to the supply pins, provide a clean low-impedance VREF (the ADC12032 expects an external +2.5 V to +5 V reference), and allow the calibration cycle to complete (tCAL ~2800 clock cycles) before issuing the first conversion command to guarantee specified accuracy. This page synthesizes TI datasheet parameters, distributor pricing, package cross-references, and practical design guidance not aggregated in any single source on the web.
ADC12034CIN/NOPB - 12-Bit+Sign 4-Ch SAR ADC | Texas Instruments
The Texas Instruments ADC12034CIN/NOPB is a self-calibrating 12-bit plus sign successive-approximation analog-to-digital converter with 4-channel input MUX, sample-and-hold, and serial MICROWIRE-compatible interface, delivering up to 182 kSPS in a 24-pin PDIP through-hole package. Per the datasheet title block, the device integrates a 2/4-input analog MUX, a precision SAR ADC core with on-chip self-calibration, and a synchronous serial data interface, allowing one part to replace multi-ADC systems in multiplexed data-acquisition designs. An SAR (Successive Approximation Register) ADC is a class of analog-to-digital converter that uses an iterative binary search against a precision DAC to resolve each conversion in N+1 clock cycles. SAR ADCs sit in the broader taxonomy of Nyquist-rate data converters, between flash converters (fast, low resolution) and sigma-delta converters (high resolution, lower bandwidth). Within TI's data-converter portfolio, the ADC12034 belongs to the ADC12030/ADC12H030 family, distinguished by their on-chip calibration logic and sign-bit output that doubles the effective dynamic range for bipolar sensor signals without an external front-end op-amp. Key features include 12-bit plus sign resolution (effectively 13 bits of dynamic range), 4 single-ended or 2 differential analog input channels multiplexed at the ADC core, self-calibration of offset and gain on command, a serial MICROWIRE/QSPI/SPI-compatible digital interface, and an operating temperature range of -40C to +85C. The on-chip sample-and-hold acquires inputs in approximately 1.2 us, while the successive-approximation engine completes conversion in 13 clock cycles, giving a maximum throughput of 182 kSPS when clocked at the rated frequency. The ADC12030 family was architected around a charge-redistribution DAC array using thin-film polysilicon resistors, calibrated at power-up or on demand via the CAL pin. After calibration, the typical INL is held within +/- 1 LSB and DNL shows no missing codes at 12 bits, as documented in the manufacturer datasheet. This calibration scheme eliminates the need for external reference trimming and gives the ADC12034 stable DC performance across the full industrial temperature range. Typical applications include process-control instrumentation, multi-channel thermocouple and strain-gauge signal chains, panel-meter and weigh-scale front-ends, portable data loggers, and industrial sensor hubs where a single ADC must sequentially digitize several low-bandwidth analog sources. When selecting this part, note that the ADC12034 is offered in PDIP-24 (this part), SOIC-24 (ADC12034CIM/NOPB), and PLCC-28 (ADC12034CIQ/NOPB) variants - choose the through-hole PDIP when hand prototyping or when socket replacement is desired. Provide a clean +5V analog supply and a stable external reference; expect typical integral nonlinearity around +/-1 LSB after calibration. This page synthesizes current distributor pricing, true drop-in alternatives from the same ADC12030/ADC12038 family, and practical layout notes not aggregated in the manufacturer datasheet.
ADC12038CIWM/NOPB - 12-Bit+Sign SAR ADC, 8-Ch MUX | TI
The Texas Instruments ADC12038CIWM/NOPB is a 12-bit plus sign, self-calibrating, successive-approximation (SAR) analog-to-digital converter with a serial I/O interface, an 8-input analog multiplexer, and on-chip sample/hold, housed in a 28-pin SOIC (IWM) wide-body package. The converter family provides 12-bit resolution plus a sign bit for true bipolar input measurement, with the MUX configurable as 4 or 8 single-ended inputs or 2 differential channels, making it well suited for multi-channel data acquisition systems. A SAR ADC is a type of analog-to-digital converter that performs a binary search across an internal capacitive DAC to resolve the input voltage in one conversion cycle per bit, trading conversion speed for excellent DC accuracy and low latency. As a member of the data converter (ADC) class, it sits within the hierarchy: SAR ADC -> ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Self-calibration architecture automatically corrects internal capacitor mismatch and zero-scale/gain errors at power-up or on demand, achieving the 12-bit specified accuracy without user adjustments. Key features include 12-bit plus sign resolution, an internal configurable MUX (8 single-ended or 4 differential inputs), self-calibration, a serial interface compatible with SPI/QSPI/MICROWIRE, a 28-pin SOIC wide-body (IWM) industrial-temperature package, and an operating range of -40 C to +85 C. The device runs from a single +5 V analog supply with low power consumption, making it appropriate for portable and distributed data acquisition nodes. The serial I/O reduces pin count versus parallel-output ADCs and simplifies board routing in dense multi-channel designs. Built-in sample/hold eliminates the need for an external track-and-hold amplifier, and the sign bit plus bipolar input capability allow direct measurement of signals swinging around ground without level shifting. Typical applications include multi-channel industrial process control, portable instrumentation, weigh scales, temperature monitoring with thermocouple/RTD front ends, and battery management telemetry. The 8-input MUX enables one ADC to scan multiple sensor channels, reducing system cost and PCB area. When designing with this part, provide a clean +5 V analog supply and a low-impedance reference. Decouple the analog supply pin close to the IC with a 0.1 uF ceramic in parallel with a 10 uF tantalum or ceramic bulk capacitor, and keep the reference pin similarly bypassed. Maintain analog and digital grounds with a single-point tie to avoid coupling digital switching noise into the converter's reference. This page synthesizes distributor pricing, drop-in alternatives drawn from the TI ADC12030/ADC12H030 family, and practical design notes that complement the manufacturer datasheet.
ADC12040CIVY - 12-Bit 40MSPS Pipelined ADC | Texas Instruments
The Texas Instruments ADC12040CIVY is a 12-bit, 40 MSPS pipelined analog-to-digital converter with internal sample-and-hold, supplied in a 32-pin LQFP (NEY) package measuring 7x7 mm. The device operates from a single +5V supply with ±5% tolerance, dissipating only 340 mW typical at 40 MHz sampling rate and providing CMOS-compatible digital outputs from 2.35V to 5V. The differential inputs support a full-scale swing equal to 2*VREF, accepting both single-ended and differential analog inputs while exploiting the differential input for optimum dynamic performance. An analog-to-digital converter (ADC) is a data-converter integrated circuit that samples continuous-time analog signals and produces discrete-time digital codes. Within the data-converter hierarchy, ADCs sit alongside DACs (digital-to-analog converters), and the pipelined ADC architecture used in the ADC12040 is one of the most popular for medium-to-high sampling rates (10 MSPS to several hundred MSPS) because it balances high throughput, low power, and small die area better than flash or SAR alternatives. Pipeline ADCs use multiple cascaded low-resolution stages with digital error correction, and the architecture scales efficiently with bit count. Key specifications include ±0.4 LSB typical differential non-linearity (DNL), 69 dB typical signal-to-noise ratio (SNR) at fIN = 10 MHz, and 11.2 bits typical effective number of bits (ENOB) at the same input frequency. The integrated reference buffer eliminates the need for external reference buffering, and an on-chip power-down mode reduces consumption to microamp levels between conversions. Pin compatibility with the ADC12010, ADC12020, ADC12L063, and ADC12L066 simplifies migration between speed grades within the same family. The device uses a CMOS pipeline core with an internal sample-and-hold and a selectable single-ended or differential input path. A buffered, high-impedance single-ended reference input is converted on-chip to a differential reference for the processing chain, simplifying PCB layout. Output data format is straight binary, and the parallel interface easily interfaces with FPGAs, ASICs, or microcontrollers. Typical applications include IF sampling in communications receivers, ultrasound imaging front-ends, CCD digitizers, video digitizing, and portable instrumentation. The 40 MSPS rate is sufficient for baseband I/Q capture in narrowband radios and for time-domain analysis up to ~20 MHz of analog bandwidth when undersampling or full Nyquist operation is desired. When designing with this part, route analog inputs as a 50-ohm matched differential pair and bypass the +5V supply with a 10uF tantalum plus 0.1uF ceramic decoupling network within 5 mm of the supply pin. Use a low-impedance analog ground plane and keep digital outputs away from the analog inputs to preserve SNR. This page synthesizes distributor pricing, drop-in alternatives and practical design notes beyond what the manufacturer datasheet alone provides.
ADC12041CIMSAX - 12-Bit+Sign 216kHz 8-Ch SAR ADC | Texas Instruments
The Texas Instruments ADC12041CIMSAX is a 12-bit plus sign, 216 kHz sampling, 8-channel input, self-calibrating successive-approximation analog-to-digital converter (SAR ADC) housed in a 28-pin SSOP package. It operates from a single +5V analog supply (VA+ = VD+ = 5V), supports a reference range up to 4.096V (VREF+) and 0V (VREF-), and uses a parallel digital interface for high-throughput data transfer. The eight input channels feed a fully differential analog multiplexer, enabling flexible multi-channel data acquisition on a single mixed-signal IC. A SAR ADC is a type of analog-to-digital converter that uses a binary-search successive-approximation algorithm against an internal capacitive DAC to digitize each input sample in N clock cycles (where N is the resolution in bits). The 12-bit+sign architecture extends the dynamic range to 13 bits total, allowing bipolar signal measurement with a single-ended or differential input and a fixed common-mode voltage (e.g. 2.048V at VREF+ = 4.096V). Self-calibration routines correct internal capacitor mismatch at power-up and on demand, holding DC linearity tight across temperature. Key features include a maximum sampling rate of 216 kHz, a 12-bit + sign output word (13 bits of resolution), eight input channels through a fully differential MUX, an fCLK of up to 12.0 MHz external clock, on-chip self-calibration, and a single +5V supply operation. The self-calibration routine and differential MUX architecture eliminate most external front-end analog conditioning, allowing the part to drop into compact data-acquisition front ends. The ADC12041 uses a charge-redistribution SAR core with a built-in calibration register that trims zero-scale and full-scale errors. The device accepts either unipolar (0 to VREF) or bipolar (-VREF to +VREF) input ranges when configured in the appropriate mode, and the +sign bit is appended to the 12-bit two's complement output word, simplifying downstream signal processing for both AC and DC measurements. Typical applications include multi-channel industrial process control, portable instrumentation and data loggers, medical patient monitoring front ends, automotive sensor multiplexing, factory automation I/O modules, and any high-accuracy multi-channel measurement system that needs a parallel digital interface to a host microcontroller or DSP. When designing with this part, place the 0.1 uF supply bypass capacitors as close as possible to VA+ and VD+ and keep VREF trace impedance low (RS <= 1 ohm) to preserve linearity. The internal calibration sequence requires a stable clock and reference at startup; allow at least 1 ms of settling after power-up before initiating the first conversion. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical PCB-level design guidance that complements the National Semiconductor / TI datasheet.
ADC12048CIVF/NOPB - 12-Bit+Sign 216kHz 8-Ch SAR ADC | TI
The Texas Instruments ADC12048CIVF/NOPB is a 12-bit plus sign, 216 kHz, 8-channel, self-calibrating successive-approximation-register (SAR) analog-to-digital converter (ADC) housed in a 44-pin PQFP (10x10 mm) package. The part operates from a single 5 V analog supply and a separate 5 V digital supply, samples up to eight fully differential analog inputs through an internal multiplexer, and outputs conversion data through a 12-bit + sign parallel interface. The /NOPB suffix indicates the lead-free, matte-tin finish that meets RoHS requirements. The device is offered in the industrial temperature range of -40C to +85C, making it suitable for commercial and industrial process-control and instrumentation applications. A SAR ADC (Successive-Approximation-Register analog-to-digital converter) is a class of Nyquist-rate data converter that uses a binary-search algorithm to digitize an analog input in N clock cycles, where N is the resolution. SAR ADCs are valued for their deterministic latency, low power consumption, and excellent DC accuracy with no pipeline delay, which makes them the architecture of choice for multiplexed multi-channel data-acquisition systems, motor control feedback, and instrumentation front ends. The ADC12048 belongs to the broader hierarchy of analog-to-digital converters (ADCs) -> data converters -> signal-chain ICs -> mixed-signal semiconductors. Key features include 12-bit + sign resolution (effectively 13-bit dynamic range), an 8-input analog multiplexer (configurable as 4 differential or 8 single-ended channels), self-calibration for offset and gain, a track-and-hold front end, and a sampling throughput of up to 216 kilosamples per second (kSPS). The wide dynamic range and differential input capability make the ADC well-suited to digitizing small transducer signals in noisy industrial environments without external instrumentation amplifiers. Parallel output simplifies the digital interface and removes SPI/I2C timing overhead at the cost of wider board routing. The architecture combines a capacitive charge-redistribution DAC with the SAR logic and an on-chip track-and-hold amplifier, and it provides self-calibration and user-initiated calibration modes to maintain specified accuracy across temperature. The internal MUX and reference input structure together with the parallel output interface allow the part to serve as a complete data-acquisition front end in a single 44-pin surface-mount IC, replacing multi-chip discrete solutions and reducing board space. Typical applications include industrial process control, multi-channel data-acquisition systems, motor control position and current feedback, patient monitoring instrumentation, and battery-cell monitoring in UPS and telecom systems. Specific scenarios include PLC analog input modules, multi-axis servo drives, and remote sensor hubs requiring 8 simultaneous analog channels at moderate throughput. When designing with this part, ensure that the analog and digital supplies are properly decoupled and that the analog input common-mode voltage is within the specified range; note that the reference voltage determines full-scale accuracy and must be stable to realize the device's rated performance. Use the self-calibration mode at power-up and after any significant temperature change. This page synthesizes distributor pricing, drop-in compatible alternatives, and practical design notes that go beyond a single datasheet summary to help you select and source the ADC12048CIVF/NOPB with confidence.
ADC1207S080HW/C1 - 12-bit 80MSPS ADC | NXP HTQFP-48
The NXP ADC1207S080HW/C1 is a single-channel, 12-bit resolution analog-to-digital converter (ADC) optimized for direct IF sampling in ultra-high-IF radio transceiver architectures, sampling up to 80 MSPS with parallel CMOS-compatible digital output. It integrates a high-bandwidth differential track-and-hold front end, on-chip reference, and a parallel LVCMOS/CMOS output bus in a 48-pin HTQFP (7x7 mm) exposed-pad package suitable for surface-mount industrial designs. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a specified sampling rate. Single-channel pipelined ADCs sit within the hierarchy of data converters -> mixed-signal ICs -> signal chain ICs -> semiconductors, and serve as the analog front-end bridge between RF/IF analog sections and downstream digital signal processing (DSP) blocks. ADC1207S080HW/C1's 12-bit/80 MSPS positioning targets intermediate-frequency (IF) sampling where the analog input has already been mixed down from RF but still occupies tens of MHz of bandwidth, eliminating the need for an additional down-conversion stage. Key features include a 12-bit resolution, 80 MSPS maximum sampling rate, single 1.4 Vpp differential or 1.4 Vpp single-ended analog input range, integrated bandgap reference, low-latency parallel digital interface, and an extended industrial operating temperature range of -40C to +85C. The HTQFP-48 (7x7) exposed-pad package provides low thermal resistance and supports both reflow soldering and standard PCB assembly, with the exposed pad providing both thermal dissipation and a low-impedance ground return for the analog front end. The ADC1207S080HW/C1 architecture uses a multi-stage pipelined core with digital error correction, sample-and-hold input, and an internal reference with optional external override. The wide input bandwidth supports direct sampling of IF signals well above the Nyquist limit (IF undersampling), reducing system BOM cost by eliminating mixer stages. Output coding is straight binary with a separate output enable pin for bus-sharing among multiple ADCs on the same parallel bus. Typical applications include software-defined radio (SDR) receiver IF digitizers, broadband cable infrastructure downstream receivers, radar and electronic-warfare intermediate-frequency stages, medical imaging signal chains, and high-speed industrial instrumentation such as oscilloscopes and spectrum analyzers. Designers select the ADC1207S080HW/C1 when the input is already in the tens-of-MHz range and the downstream DSP or FPGA requires 12-bit native resolution at sample rates up to 80 MSPS. When designing with this ADC, prioritize clock jitter performance: the SNR at 80 MSPS is sensitive to broadband aperture-jitter, so use a low-phase-noise clock source (e.g., a dedicated clock generator with sub-ps RMS jitter) and keep the clock trace short and impedance-controlled. Bypass the analog supply pins with 100 nF ceramic capacitors placed within 2 mm of each pin, and tie the exposed pad to a clean analog ground island. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, with pricing and lifecycle data refreshed as of 2026-10-12.
ADC1207S080HW/C1:1 - 12-Bit 80 MSPS ADC, Parallel IF-Sampling | NXP
The NXP ADC1207S080HW/C1:1 is a single-channel, 12-bit analog-to-digital converter (ADC) optimized for direct intermediate-frequency (IF) sampling, supporting up to 80 MSPS conversion rates. Housed in a 48-pin HTQFP (7 mm × 7 mm) package with an exposed thermal pad, this ADC delivers high dynamic performance in demanding wireless-infrastructure, optical-networking, and fixed-telecom receiver chains. The C1:1 suffix denotes the tape-and-reel (TR) packaging option from NXP USA Inc., shipped as the production variant per the official DigiKey catalog listing. An ADC is a mixed-signal integrated circuit that converts continuous analog voltage into discrete digital codes at a rate set by its sampling clock. High-IF ADCs such as the ADC1207S080 family are engineered for direct RF/IF digitization, eliminating one or more down-conversion mixer stages by undersampling broadband IF signals. They sit in the signal-processing hierarchy between the front-end analog filter and the digital baseband processor, making their spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) decisive for receiver sensitivity in cellular base stations and software-defined radio platforms. Key differentiating specifications of the ADC1207S080HW/C1:1 include a 12-bit resolution with 80 MSPS maximum sample rate, LVCMOS-compatible digital outputs, and a programmable Complete Conversion Signal (CCS) feature that allows fine-grained adjustment of the acquisition-clock edge for clean signal alignment in the stable data window. The DEL0 and DEL1 logic inputs shift the CCS edge to avoid metastable boundaries, a critical capability in multi-board synchronous systems such as GSM, LTE, and WCDMA base-station receivers where exact timing skew between parallel data lanes is mandatory. Architecturally, the converter is a single-core pipelined design supplied by a single 3.0 V–3.6 V analog supply and 1.4 V–3.6 V digital supply (per NXP datasheet family), with parallel CMOS outputs and a 48-lead HTQFP exposed-pad package that provides low thermal resistance. Internal calibration tracks gain and offset drift, sustaining ENOB across the full -40 °C to +85 °C industrial temperature range. The part is manufactured by NXP USA Inc. (formerly Freescale/IDT) using a standard CMOS process. Typical applications include cellular-infrastructure IF sampling, optical-networking transponder digitizers, fixed-telecom line cards, broadband software-defined radio front ends, instrumentation IF digitizers, and medical-ultrasound beamformer ADCs. In each of these use cases, the 80 MSPS/12-bit combination delivers the SFDR and SNR required for high-IF direct-sampling architectures. When designing with this part, pay careful attention to PCB layout of the analog and digital supplies; the exposed pad must be soldered to a continuous ground plane for both thermal dissipation and noise isolation. The CCS delay settings (DEL0/DEL1) must be tuned per board to avoid data-valid-window violations. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving buyers and design engineers a single source of truth for sourcing, second-sourcing, and PCB-level integration decisions.
ADC1207S080HW/C1:5 - 12-Bit 80MSPS Single-Channel ADC | NXP
The NXP ADC1207S080HW/C1:5 is a 12-bit, 80 MSPS single-channel analog-to-digital converter optimized for direct IF sampling in ultra-high-IF radio transceivers, housed in a 48-pin HTQFP (7x7 mm) exposed-pad package. It delivers 80 megasamples per second through a parallel CMOS-compatible data interface, supports a single analog input, and operates from 5V analog and digital supplies. The part is specified for the industrial -40C to +85C temperature range and ships in tray packaging. An ADC (Analog-to-Digital Converter) is a mixed-signal data-conversion IC that quantizes continuous analog voltages into discrete digital codes, sitting between sensors/antennas and downstream DSP or FPGA blocks in the signal chain hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Pipeline ADCs like the ADC1207S080HW/C1:5 specifically use a switched-capacitor architecture to achieve tens-to-hundreds of MSPS with low latency, making them the workhorse for IF sampling in communications infrastructure. Key features include 12-bit native resolution, 80 MSPS maximum sampling rate, internal reference voltage, single-ended analog input, and parallel CMOS data interface. The 48-HTQFP exposed-pad package provides low thermal resistance and a small PCB footprint. Two logic inputs, DEL0 and DEL1, allow the user to trim the edge position of the clock-duty-cycle-stabilized (CCS) output signal to place it inside the stable data-eye window. The architecture uses a multi-bit-per-stage switched-capacitor pipeline with on-chip sample-and-hold, internal bandgap reference, and digital error correction. The integrated clock-duty-cycle stabilizer relaxes PCB-level clock-routing constraints, while the parallel interface removes the need for a deserialization FPGA block in low-channel-count systems. The exposed thermal pad allows the die to dissipate heat efficiently when sampling wide-bandwidth IF signals. Typical applications include direct-IF sampling for software-defined radio receivers, LTE/3G/4G base-station receivers, radar and electronic-warfare front ends, medical ultrasound beamformers, and high-speed instrumentation digitizers. The 80 MSPS rate is well-matched to second-IF or near-baseband demodulation in zero-IF or low-IF receivers where the ADC directly digitizes a tens-of-MHz IF. When designing with this part, keep analog and digital ground planes separate and join them only at the exposed pad; use short-form-current-mode clock-runner traces and a clean low-jitter clock to preserve SNR. Drive the analog input through a properly bandwidth-limited differential driver (or single-ended buffer) and follow the datasheet's decoupling network exactly to avoid degrading ENOB. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
ADC1210S065HN/C1 - 12-bit 65 MSPS ADC, LVDS/CMOS, HVQFN-40 | Renesas
The Renesas (formerly NXP/IDT) ADC1210S065HN/C1 is a single-channel 12-bit pipelined Analog-to-Digital Converter (ADC) that samples at 65 MSPS and supports both CMOS and LVDS DDR digital outputs, housed in a 40-pin HVQFN (6 x 6 mm, 0.85 mm height, SOT618-1) package. The -C1 ordering suffix denotes a specific tape-and-reel/reel-pack quantity option from the same silicon. Industrial temperature grade parts use the /C1 :5 tray/reel suffix convention. According to the manufacturer datasheet, this ADC is part of the ADC1210S family which spans 65, 80, 105, and 125 MSPS speed grades, all pin-compatible so designers can re-validate a single PCB across a wide performance range. An ADC (Analog-to-Digital Converter) is a data acquisition integrated circuit that converts continuous analog input signals into discrete digital codes at a defined sampling rate, sitting at the boundary between the analog front end and the digital signal chain within a data acquisition system. Pipelined ADCs like the ADC1210S use multiple low-resolution flash stages to deliver high sample rates (tens to hundreds of MSPS) at moderate resolution (8-14 bits), making them the workhorse of communications, imaging, and test-and-measurement equipment where bandwidth, not absolute DC linearity, is the primary requirement. The ADC1210S065HN/C1 features 12-bit resolution, a 65 MSPS maximum sampling rate, selectable CMOS or LVDS DDR output modes, and an internal reference, reducing the bill of materials for typical system designs. The HVQFN-40 package provides an exposed thermal pad for low thermal resistance, which is critical for industrial-grade continuous sampling. Operating from a single 1.8 V analog supply and a separate 1.8 V or 3.3 V digital output supply, the device simplifies multi-rail system design. The 12-bit linearity and SNR are tuned for IF-sampling and high-speed instrumentation use cases. Typical applications include communications IF/baseband digitization, industrial imaging and machine vision, ultrasound receive-channel front ends, portable oscilloscopes and digitizers, and software-defined radio. When designing with this device, place the analog input network (transformer or differential driver) within 5 mm of the input pins and provide a solid ground pour stitched with vias around the exposed pad to keep the SNR within datasheet limits. Match LVDS output trace lengths (within 5 mil) for the DDR clock and data pairs to preserve timing margins.
ADC1210S105HN/C1:5 - 12-Bit 105 Msps ADC, CMOS/LVDS DDR | NXP
The NXP ADC1210S105HN/C1:5 is a single-channel 12-bit pipelined analog-to-digital converter sampling up to 105 Msps with selectable CMOS or LVDS DDR digital outputs, packaged in a 40-pin HVQFN (6x6 mm, 0.85 mm height) with exposed thermal pad. It accepts one analog input, integrates on-chip reference and clock duty-cycle stabilizer, and operates across an industrial -40C to +85C temperature range. A pipelined analog-to-digital converter (ADC) is a high-speed Nyquist-rate data converter that resolves an analog input into a digital code through multiple cascaded low-resolution stages, each driving a residue amplifier into the next stage. In the broader signal-chain hierarchy, ADCs sit between the analog front-end (amplifiers, filters, drivers) and the digital back-end (FPGA, ASIC, microcontroller), where they convert real-world signals such as IF, video, imaging, or industrial sensor outputs into binary words for processing. Pipelined ADCs dominate the 40-250 Msps performance window because they combine high sampling rate with moderate resolution (10-14 bits) at low power per conversion. Key features of the ADC1210S105HN/C1:5 include a 105 Msps maximum sample rate, 12-bit resolution, single analog input channel, a choice of parallel CMOS or LVDS DDR digital interfaces, internal bandgap reference with optional external reference override, and a clock duty-cycle stabilizer that tolerates non-50% input clock duty cycles. The 6x6 mm HVQFN-40 footprint preserves board area while the exposed pad keeps junction temperature low at full conversion rate. The device is part of a broader speed-grades family spanning 65, 80, 105, and 125 Msps from the same silicon. Typical applications include IF/baseband digitization in wireless infrastructure, medical imaging front-ends (ultrasound beamformers), industrial test and measurement digitizers, defense signal-intelligence receivers, and high-speed data acquisition systems for instrumentation. In each case the ADC1210S105HN/C1:5 occupies the boundary between analog signal conditioning and digital signal processing. When designing the analog input network, drive the AIN pin with a low-impedance differential or single-ended amplifier and provide proper anti-alias filtering before the sampler. Decouple AVDD and DVDD rails close to the package and tie the exposed pad to a clean analog ground plane to manage thermal dissipation at full 105 Msps. This page synthesizes distributor pricing, drop-in compatible 65/80/125 Msps speed-grade alternatives, and practical PCB layout guidance not found in the bare manufacturer datasheet.
ADC1210S125HN/C1:5 - 12-bit 125MSPS ADC | NXP
The NXP ADC1210S125HN/C1:5 is a single-channel 12-bit pipelined Analog-to-Digital Converter sampling at 125 MSPS with selectable CMOS or LVDS DDR digital outputs, housed in a 40-pin HVQFN (6x6 mm) package. It supports a 1.4 V internal reference (or external reference option), differential or single-ended analog inputs, and an operating temperature range of -40C to +85C. The architecture combines a high-bandwidth track-and-hold front end with multi-stage pipelined quantization and on-chip digital error correction, achieving spurious-free dynamic range and signal-to-noise figures typical of mid-speed 12-bit converters. An Analog-to-Digital Converter (ADC) is a mixed-signal data-acquisition component that translates continuous analog voltages into discrete digital codes for processing by FPGAs, DSPs, microcontrollers, or ASICs. Within the broader product hierarchy, the ADC1210S125HN/C1:5 is a high-speed pipelined ADC, a sub-category of Nyquist-rate data converters used in communications, imaging, and instrumentation. The pipelined topology balances conversion speed and power efficiency by partitioning conversion across cascaded low-resolution stages, with the trade-off of a fixed number of clock-cycle latency that simplifies digital host synchronization. Key features include user-selectable 65, 80, 105, or 125 MSPS operation, flexible CMOS/LVDS DDR output modes for FPGA/ASIC interface compatibility, internal bandgap reference with external override, and built-in input common-mode adjustment for transformer-coupled or single-ended drive. The 40-HVQFN package with exposed pad (SOT618-1 / MO-220) gives thermal resistance low enough to handle typical dissipation without external heatsinking. Typical applications are high-density medical imaging front ends, cable DOCSIS edge digitizers, wireless IF baseband receivers, and radar/sonar pre-processing channels. The pipelined latency and DDR outputs are well-suited to FPGA-based digital downconversion. When designing with this part, route analog inputs as 50 ohm differential microstrip with controlled impedance, place the decoupling capacitors within 2 mm of the supply pins, and follow the datasheet layout guidance for the exposed pad (EP) thermal connection to a continuous ground plane.
ADC1212D125HN-C1 - Dual 12-bit 125MSPS ADC, LVDS/CMOS | Renesas
The Renesas ADC1212D125HN-C1 is a dual-channel 12-bit pipelined analog-to-digital converter (ADC) optimized for high dynamic performance and low power consumption at sample rates up to 125 Msps. It is housed in a 64-pin HVQFN (9 x 9 mm, 0.85 mm height, SOT804-3) package and supports both CMOS and LVDS DDR digital output interfaces for flexible system integration. A pipelined ADC is a type of analog-to-digital converter that uses a cascaded chain of low-resolution flash stages to digitize analog signals at high sampling rates. The pipelined architecture occupies the middle ground between low-speed successive-approximation (SAR) ADCs and very-high-speed flash ADCs, making it the workhorse for communications, imaging, and test-and-measurement applications. Dual-channel pipelined ADCs like the ADC1212D125HN-C1 further integrate two converter cores on one die, allowing simultaneous sampling of two signals (typical in I/Q baseband, diversity receivers, or multi-antenna systems) while sharing reference, clock, and digital interface circuitry. Key features include 125 Msps maximum conversion speed, 12-bit resolution across two channels, and selectable CMOS or LVDS DDR output modes. The device operates from a 1.8V analog supply and 3.3V digital supply, with a wide input common-mode range suited to AC-coupled or DC-coupled front ends. Built-in features such as a programmable gain amplifier, internal reference, and flexible clock input simplify board-level design. The architecture uses a multi-stage pipeline with proprietary error-correction logic to maintain linearity and spurious-free dynamic range (SFDR) performance. The dual digital-output paths can be configured as two independent CMOS ports or a single LVDS DDR pair, giving system designers a choice between low-EMI board routing (LVDS) and direct connection to legacy logic (CMOS). Typical applications include wireless base-station receivers, radar and lidar signal chains, medical imaging front ends, communications test equipment, and high-speed data acquisition systems. The wide bandwidth of the analog input and the dual-core integration make it suitable for I/Q demodulation in software-defined radio (SDR) platforms. When designing with this device, ensure the analog and digital grounds are partitioned carefully and that the input is driven by a low-impedance differential amplifier to fully realize the SFDR. Decoupling must follow manufacturer recommendations with close-proximity 100nF + 10uF combinations on each supply pin. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, helping engineers select and source the ADC1212D125HN-C1 with confidence for high-speed signal-chain designs.
ADC12130CIN/NOPB - 12-bit+Sign SAR ADC w/MUX | TI
The Texas Instruments ADC12130CIN/NOPB is a self-calibrating 12-bit-plus-sign successive-approximation analog-to-digital converter (SAR ADC) with a built-in 2-channel analog multiplexer and sample/hold, presented in a 16-pin PDIP (N) through-hole package. It provides single +5V supply operation, a serial I/O interface, and 1 LSb maximum differential nonlinearity, making it suitable for industrial-grade precision data acquisition applications. An SAR ADC is a type of analog-to-digital converter that uses a binary search algorithm implemented with a capacitive charge-redistribution DAC to digitize an analog input one bit per clock cycle. Each conversion takes a fixed number of clock cycles - in this case typically 13 to 14 clocks - giving SAR ADCs deterministic latency that is desirable in multiplexed control loops. The on-chip multiplexer allows two single-ended or one pseudo-differential input to be selected without external analog switches, while the sample-and-hold captures the input voltage at the start of conversion and holds it steady throughout the successive-approximation cycle. As a precision data converter IC, the ADC12130CIN/NOPB sits in the broader hierarchy of: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Key specifications highlighted in the manufacturer datasheet include 12-bit-plus-sign resolution (effectively 13 bits of signed dynamic range), self-calibration of internal offsets and gain, and a serial (rather than parallel) data output that reduces the host-side pin count to a few digital lines. Industrial temperature grade (-40C to +85C) and through-hole PDIP packaging further position the part for legacy and through-hole PCB designs in industrial control equipment. The serial interface frees up board space versus equivalent parallel-output ADCs, particularly valuable in cost-sensitive multiplexed sensor systems where many analog signals must be sampled sequentially. Typical applications for the ADC12130CIN/NOPB include industrial process control instrumentation, multi-channel sensor monitoring, panel meters and digital multimeters, portable data loggers, and embedded control modules that need on-board ADC functionality with minimal microcontroller pin overhead. The internal MUX lets two sensors share one ADC, while the self-calibration feature reduces drift over temperature and time, important in long-life industrial installations. When designing with this ADC, ensure that the analog input pin is driven by a low-impedance source during the acquisition window and that the serial clock and chip-select timing follows the manufacturer datasheet timing diagram. Decouple VDD with a 0.1 uF ceramic capacitor placed close to the supply pin, and consider a small RC filter at the analog input to limit broadband noise.
ADC12130CIWM - 12-Bit+Sign SAR ADC, 2-Ch MUX, Serial I/O | TI
The Texas Instruments ADC12130CIWM is a self-calibrating 12-bit plus sign successive approximation register (SAR) analog-to-digital converter with 2-channel analog input multiplexer and integrated sample-and-hold, housed in a 16-pin SOIC Wide (DW) package. Per the TI datasheet, it converts at up to 114 kSPS, communicates through an MICROWIRE-compatible serial interface, and runs from a single +5V analog supply with a separate +5V (or +3.3V) digital supply for low-noise digital isolation. A SAR ADC is a type of data converter that uses a binary-search successive-approximation algorithm combined with an internal DAC to digitize an analog input one code per clock cycle. It belongs to the ADC -> data converter -> signal chain IC -> mixed-signal semiconductor hierarchy. SAR ADCs are widely preferred when applications demand deterministic latency, low power, no pipeline delay, and moderate sample rates (10 kSPS to 1 MSPS), making them a workhorse for industrial sensors, instrumentation, and process control. Key differentiating specifications: 12-bit plus sign resolution (effectively 13 bits of dynamic range with bipolar input), built-in 2-channel input MUX for differential or single-ended measurements, self-calibration that nulls offset and linearity errors at power-up, and a serial MICROWIRE interface that reduces pin count versus parallel ADCs. The Wide part maintains roughly two microamps typical supply current in operating mode and supports -40C to +85C industrial temperature range. From an architecture standpoint, the device uses a charge-redistribution DAC array with a comparator and SAR logic, plus on-chip calibration registers that compensate for internal errors after each power-on reset. The two analog inputs can be configured as two single-ended channels or one fully differential pair, and the digital serial port can be clocked up to approximately 10 MHz, supporting both standalone microcontrollers and DSPs. Typical applications include industrial process control loops, weigh scales and load cell digitizers, portable battery-powered instrumentation, panel meters, multichannel data loggers, and temperature or pressure sensor signal chains where the built-in MUX and bipolar true-ground measurement are available. Design tip: provide a clean analog ground plane separated from the digital ground and tie them only at the AGND pin. Decouple VA+ with a 10 uF tantalum in parallel with a 0.1 uF ceramic placed within 5 mm of the pin; insufficient bulk capacitance is the most common cause of conversion noise on this part. The serial interface lines (CS, SCLK, DOUT) should be routed away from the analog inputs to avoid digital coupling. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ADC12130CIWMX - 12-Bit+Sign SAR ADC w/ MUX | Texas Instruments
The Texas Instruments ADC12130CIWMX is a self-calibrating 12-bit plus sign successive approximation register (SAR) analog-to-digital converter with serial I/O, an integrated configurable input multiplexer, and an on-chip sample-and-hold, housed in a 16-pin wide-body SOIC (DW) package. The device accepts 1 or 2 input channels via the multiplexer, supports a serial digital interface, and operates across an analog supply range compatible with industrial temperature operation from -40C to +85C. According to the manufacturer datasheet, the converter provides self-calibration for low offset and gain error, which is critical for precision measurement applications. A SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a type of analog-to-digital converter that uses a binary search algorithm and a single high-precision comparator to convert an analog input to a digital code, balancing speed, accuracy, and power consumption. SAR ADCs sit in the hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor, and are widely used in industrial process control, data acquisition systems, and instrumentation where a single conversion per acquisition is required rather than continuous streaming. Key features of the ADC12130CIWMX include 12-bit plus sign resolution (effectively 13 bits of dynamic range with bipolar input), built-in self-calibration for low offset and gain error, a 2-channel analog input multiplexer, an integrated sample-and-hold amplifier, and a serial digital output for low pin-count board design. The wide-body SOIC-16 package is drop-in compatible with the rest of the ADC12130/ADC12132/ADC12138 family. The architecture uses a charge-redistribution DAC combined with a precision comparator, with the self-calibration cycle trimming the input offset and linearity error on demand. This self-calibration corrects the gain and offset drift that would otherwise dominate total unadjusted error in standard SAR designs, providing measurement stability over temperature and time. Typical applications include industrial process control, portable instrumentation, data acquisition systems, battery-powered measurement equipment, and sensor signal conditioning. The integrated MUX and sample-and-hold reduce external component count, making it well suited for multi-channel low-bandwidth measurement front ends. When designing with this device, ensure the analog and digital supplies are properly decoupled and that the reference voltage is low-noise and stable; the ADC's linearity and noise performance are directly tied to reference quality. The self-calibration routine should be issued at power-up and after significant temperature changes for best accuracy. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing a single reference for sourcing, replacement, and application guidance.
ADC12132CIMSA - 12-Bit+Sign Self-Cal SAR ADC, 2-Ch MUX | TI
The Texas Instruments ADC12132CIMSA is a 12-bit plus sign self-calibrating successive-approximation-register (SAR) analog-to-digital converter with a 2-channel input multiplexer and integrated sample-and-hold, housed in a 20-pin SSOP package. It supports a maximum sampling rate of 114 ksps, accepts 1 or 2 single-ended (or 1 differential) analog inputs, and communicates through a MICROWIRE-compatible serial interface. The device operates from a single +3.3V or +5V supply and features on-chip self-calibration that corrects offset and linearity errors at power-up or on demand. An SAR ADC is a successive-approximation analog-to-digital converter that uses an internal binary search algorithm and a high-precision comparator to digitize an analog input one bit per conversion clock. SAR ADCs sit in the broader analog-to-digital converter family alongside delta-sigma, pipeline, and flash ADCs; they offer an attractive trade-off among resolution (8-18 bits typical), sampling rate (10 ksps to 10 Msps), latency (single-cycle deterministic), and power consumption (sub-milliwatt to tens of milliwatts). The ADC12132 specifically targets industrial instrumentation, process control, and portable data-acquisition front-ends where 12-bit resolution, an input multiplexer, and serial output are sufficient. Key specifications include 12-bit plus sign (13-bit effective) resolution, 114 ksps maximum throughput, ±1 LSB INL (max), a 3 V to 5.5 V analog supply range, low power consumption of approximately 6 mW at 5 V, and on-chip self-calibration that re-zeroes the ADC at power-up or on command. The integrated 2-channel analog multiplexer accepts either two single-ended or one differential input, eliminating the need for an external analog switch. The MICROWIRE/QSPI/DSP-compatible serial interface simplifies connection to virtually any microcontroller or DSP. The architecture is a charge-redistribution SAR core with on-chip calibration logic that measures and stores internal offset and gain correction coefficients in on-chip RAM, then applies them on every conversion. This auto-zeroing approach gives the part excellent DC accuracy over temperature without external trimming. The device also includes a sample-and-hold amplifier on the input, supporting input bandwidth well above the Nyquist limit for 114 ksps operation. Typical applications include industrial process control loop monitoring, portable battery-powered instrumentation, sensor signal conditioning for strain gauges or thermocouples, automotive sensor interfaces, and data-acquisition front-ends for embedded controllers. The combination of self-calibration, low power, and a small SSOP footprint suits it well for space-constrained precision analog designs. When designing with this part, pay close attention to the analog input bandwidth and source-impedance requirements; the sample-and-hold settles within a few hundred nanoseconds, so a low-impedance input buffer (op-amp follower) is recommended for source impedances above 5 kohm. Power-supply decoupling with a 10 uF tantalum plus 0.1 uF ceramic near the AVDD pin is critical because digital and analog currents are derived from the same pin on this older-generation part. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that the original National Semiconductor datasheet does not present side-by-side, making part selection and second-sourcing easier for design engineers.
ADC12138CIMSA - 12-Bit+Sign SAR ADC, 8-Ch MUX, Serial I/O | TI
The Texas Instruments ADC12138CIMSA is a self-calibrating, 12-bit-plus-sign successive-approximation analog-to-digital converter with serial I/O, an 8-input analog multiplexer, and an on-chip sample/hold, housed in a 28-pin SSOP package. It supports 8 single-ended or 4 differential input channels (plus COM), delivers 12-bit-plus-sign resolution (effectively 13 bits of dynamic range), and operates from a single 3.3V or 5V analog supply. A SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a type of data converter that performs a binary search through an internal DAC to digitize an analog input one bit at a time per clock cycle. Within the broader taxonomy, the ADC12138 belongs to the data-converter -> ADC -> SAR-ADC -> precision ADC hierarchy of mixed-signal integrated circuits, making it suitable for medium-speed, multi-channel measurements where deterministic latency and high DC accuracy are required. Key features include on-chip self-calibration that corrects offset and linearity errors at power-up or on demand, a serial interface (SPI/QSPI/MICROWIRE-compatible) that minimizes pin count on the 28-SSOP footprint, an 8-channel analog input multiplexer for sensor-scanning applications, low power consumption (typically < 5 mW at 5 V), and an industrial operating temperature range of -40 °C to +85 °C. The architecture combines a capacitive charge-redistribution DAC with a successive-approximation register and an input sample-and-hold amplifier. The self-calibration sequence stores correction coefficients on-chip so that subsequent conversions achieve specified linearity without user trimming. The serial I/O block supports daisy-chaining so multiple devices can share one SPI bus, useful for multi-MUX scanning in industrial front-ends. Typical applications include industrial process-control front ends, multi-sensor data acquisition boards, weigh scales, battery-monitoring systems, and portable instrumentation. The combination of an 8-channel input MUX, self-calibration, and serial output makes it attractive when a single host microcontroller must scan many analog sensors while keeping the BOM small. When designing with this ADC, pay attention to the analog input bandwidth and acquisition-time requirements versus the source impedance of the MUX channels. Place a 0.1 µF decoupling capacitor close to AVDD and DVDD, keep analog and digital grounds separated, and route reference and analog traces away from switching signals to preserve linearity. This page synthesizes distributor stock levels, drop-in same-package alternatives, comparison data, and practical design notes not found in the manufacturer datasheet.
ADC12138CIMSAX - 12-Bit+Sign SAR ADC, 8-Ch MUX, 28-SSOP | TI
The Texas Instruments ADC12138CIMSAX is a self-calibrating 12-bit plus sign successive-approximation analog-to-digital converter with a configurable input multiplexer, sample/hold, and serial (NSC MICROWIRE-compatible) I/O. It offers 4 or 8 analog input channels, a maximum sampling rate of approximately 114 ks/s, and is housed in a 28-pin SSOP package. The part is specified for industrial temperature operation from -40C to +85C and operates from 3.3V or 5V analog/digital supplies. An SAR (successive-approximation register) ADC is a class of analog-to-digital converter that uses a comparator and a binary-weighted digital-to-analog converter to determine each output bit one conversion cycle at a time. Within the data-converter hierarchy, the ADC12138 sits between general-purpose 8/10-bit ADCs and higher-resolution (16/18/24-bit) delta-sigma ADCs, with the differentiating features of self-calibration, an integrated analog multiplexer, and a sign bit that allows bipolar input ranges with a single supply. The MICROWIRE-style serial interface minimizes pin count for microcontroller- and DSP-based systems. Key differentiating features include 12-bit plus sign resolution (giving 13 bits of dynamic range over a bipolar input), on-chip self-calibration that removes offset and gain error without external components, a configurable 4/8-channel input multiplexer, an analog input range programmable to 0V-Vref or +/-Vref, low power consumption (typically under 30 mW at 5V), and a serial interface that is compatible with NSC MICROWIRE and most microcontroller SSP/SPI ports. The 28-SSOP footprint is a low-profile plastic package widely used in industrial instrumentation. The architecture is a classic charge-redistribution SAR with a calibrated DAC, plus a finite-state machine that runs an internal gain/offset trim after power-up. The integrated sample/hold and input MUX reduce external analog front-end complexity. Self-calibration means designers do not need to allocate analog trim pins or run system-level offset/gain compensation at every power cycle. Typical applications include multi-channel data acquisition front-ends, industrial process control sensor multiplexing, portable instrumentation with battery-supply operation, multi-point thermocouple or bridge-sensor measurement, factory-automation analog input modules, and PLC analog input cards. The 8-channel MUX is well matched to multi-sensor monitoring. When designing with this part, ensure the analog and digital supplies are decoupled with 0.1 uF ceramic capacitors placed within 5 mm of the supply pins, route the REF pin with a low-impedance ground return, and avoid running serial clock edges close to analog-input transitions to minimize digital feedthrough to the MUX output. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
ADC12138CIN/NOPB - 12-bit+Sign 8-ch SAR ADC 114ksps | TI DIP-28
The Texas Instruments ADC12138CIN/NOPB is a self-calibrating 12-bit plus sign successive approximation analog-to-digital converter with serial I/O, an 8-channel input multiplexer, and an integrated sample-and-hold, housed in a 28-pin PDIP through-hole package. It samples at 114 ksps, communicates via MICROWIRE-compatible serial interface, and operates from a single 3V to 5V analog supply with low power consumption, making it well-suited for embedded multi-channel data acquisition. What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a low-latency ADC architecture that uses an internal binary-search algorithm against a precision DAC to converge on the input voltage within N clock cycles, where N is the resolution. SAR ADCs sit hierarchically under analog-to-digital converters, data converters, signal chain ICs, and finally power management and signal-chain semiconductors. They are the dominant choice when designers need deterministic acquisition latency, no pipeline delay, and excellent DC linearity - contrast them with sigma-delta ADCs (higher resolution but heavier digital filtering) and pipeline ADCs (faster throughput at higher cost). Key features of this part include 12-bit resolution plus sign (effectively 13-bit dynamic range bipolar), a configurable 4 or 8 input channel multiplexer (part of the ADC12130/12132/12138 family), 0.0488% linearity error (about 1 LSB), 8.8 µs typical conversion time at a 114 ksps throughput, and built-in self-calibration that corrects offset and linearity errors on demand, eliminating manual trimming in production. The MICROWIRE serial interface reduces MCU pin count to three (CS, SCLK, DOUT), simplifying PCB routing in space-constrained designs. The architecture combines a charge-redistribution DAC, a high-speed comparator, and an SAR control register that performs binary-weighted approximations. Built-in self-calibration measures internal errors and applies digital correction on each conversion cycle, enabling the part to maintain 12-bit accuracy across the -40°C to +85°C industrial temperature range without user intervention. Typical applications include portable instrumentation, multi-channel sensor monitoring systems, industrial process control loops with 4-20 mA front ends, and embedded data acquisition boards that need an 8-channel analog front end behind a microcontroller. The 8.8 µs conversion time is suitable for control-loop bandwidths in the low kilohertz range. When designing with this converter, allocate ample settling time for the multiplexer stage at the analog input and add a small RC filter to attenuate broadband noise - the integrated sample-and-hold handles acquisition but a high-impedance source can introduce gain error. The single-supply operation simplifies power-rail design relative to bipolar-input ADCs that need ±5 V rails. This page synthesizes pricing tiers across authorized distributors, validated drop-in alternatives in the same PDIP-28 footprint, and practical design notes beyond the manufacturer datasheet to accelerate your evaluation of the ADC12138CIN/NOPB.
ADC12138CIWM - 12-bit+Sign 8-Ch SAR ADC, 28-SOIC | Texas Instruments
The Texas Instruments ADC12138CIWM is a self-calibrating 12-bit plus sign successive-approximation analog-to-digital converter with serial I/O, an 8-channel configurable analog input multiplexer, and an integrated sample-and-hold, housed in a 28-pin SOIC (WM) wide-body package. Per the TI datasheet, the device supports 4 differential or 8 single-ended input channels and operates from a single 3 V to 5.5 V analog supply, reaching 114 kSPS throughput while consuming approximately 1.3 mA at full speed. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog voltages and converts them into discrete binary words for processing by a microcontroller, DSP, or FPGA. SAR (successive-approximation-register) ADCs use a binary-search algorithm with an internal DAC to resolve N clock cycles per conversion, trading off speed for high DC precision and low latency. The ADC12138 family sits in the hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Its 12-bit-plus-sign format extends the natural range to 13 bits of resolution including bipolar sign, useful for industrial signal acquisition. Key features include differential nonlinearity (DNL) of +/-0.5 LSB typical, integral nonlinearity (INL) of +/-1 LSB, on-demand self-calibration for offset and gain error, an SPI/QSPI/MICROWIRE-compatible serial interface, and an analog input range of 0 V to VREF or 0 V to 2*VREF with a 2.5 V reference. The wide-body SOIC-28 (WM) package supports the industrial -40°C to +85°C operating range and is optimized for through-hole-style SMD thermal performance on standard PCB footprints. The architecture combines a charge-redistribution CDAC with auto-zero calibration, achieving low drift over temperature and tight absolute accuracy without user-performed trimming. Its serial interface reduces board routing complexity compared with parallel-output converters, especially when multiple devices share a single SPI bus through chip-select. Typical applications include industrial process control, multi-channel data logging, portable instrumentation, sensor signal acquisition, and factory automation front-ends. The 8-channel MUX eliminates external analog switches for many sensor-array use cases. When laying out this board, place the 0.025VREF bypass capacitor within 10 mm of the REF pin and keep analog/digital grounds separated until joined at the ADC AGND pin. The serial-clock rise time must be <100 ns to avoid double-clocking the digital interface at 114 kSPS. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical PCB layout guidance not found in the bare datasheet PDF.
ADC12138CIWM/NOPB - 12-Bit+Sign 8-Ch SAR ADC | Texas Instruments
The Texas Instruments ADC12138CIWM/NOPB is a 12-bit plus sign, self-calibrating, successive approximation register (SAR) analog-to-digital converter (ADC) with a configurable 8-channel input multiplexer and serial I/O, housed in a 28-pin SOIC wide-body (SOIC-28) package. According to the manufacturer datasheet, it supports sampling rates up to 114 kSPS, accepts pseudo-differential or single-ended analog inputs, and provides an SPI/serial-compatible digital interface suitable for microcontroller and DSP host connections. The integrated sample-and-hold amplifier, on-chip self-calibration logic, and ±1 LSB (max) linearity error make this part a precise data-acquisition front end for industrial instrumentation. An SAR ADC is a type of data converter that uses a binary search through successive approximation register logic to digitize an analog input one bit at a time within a single conversion cycle. The ADC12138 belongs to the broader category of successive approximation ADCs, which are valued for their low power consumption, deterministic latency, and excellent DC accuracy. Within the system hierarchy, this part sits as a precision analog front-end in a data acquisition system, performing the critical bridge between real-world analog sensors and the digital signal processor, microcontroller, or FPGA that processes the resulting codes. Self-calibration is a built-in feature that corrects internal capacitor mismatch and zero-scale/full-scale errors on demand, removing the need for manual trimming during production. Key features include 12-bit plus sign resolution (effectively 13 bits of dynamic range when measuring bipolar signals), 8 analog input channels selectable via software, a 4-channel pseudo-differential mode for noise rejection, an on-chip sample-and-hold, and self-calibration on power-up or on command. The 28-pin SOIC wide-body package provides ease of prototyping and rework, while the 3V to 5V analog supply range and 3V to 5V digital supply range simplify integration into both 3.3V and 5V systems. Typical applications include industrial process control, multi-channel data loggers, portable instrumentation, and medical monitoring where multiple sensors must be digitized with high DC accuracy. The 8-channel multiplexer is well suited to multi-zone temperature, pressure, or strain-gauge measurements where a single ADC must service many sensors. When designing with this part, place a 0.1 uF decoupling capacitor close to the analog supply pin and a 10 uF bulk capacitor on the digital supply. Use a quiet analog ground plane and route SCLK and DOUT traces away from analog inputs to minimize digital-to-analog coupling. The /CS pin enables multi-device SPI bus sharing for systems that need more than eight input channels.