ADC1210S125HN/C1:5 - 12-bit 125MSPS ADC | NXP
MPN: ADC1210S125HN/C1:5 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $29.2 | $292.00 |
| 100 | $25.8 | $2,580.00 |
| 500 | $23.4 | $11,700.00 |
| 1,000 | $21.1 | $21,100.00 |
ADC1210S125HN/C1:5 Overview
An Analog-to-Digital Converter (ADC) is a mixed-signal data-acquisition component that translates continuous analog voltages into discrete digital codes for processing by FPGAs, DSPs, microcontrollers, or ASICs. Within the broader product hierarchy, the ADC1210S125HN/C1:5 is a high-speed pipelined ADC, a sub-category of Nyquist-rate data converters used in communications, imaging, and instrumentation. The pipelined topology balances conversion speed and power efficiency by partitioning conversion across cascaded low-resolution stages, with the trade-off of a fixed number of clock-cycle latency that simplifies digital host synchronization.
Key features include user-selectable 65, 80, 105, or 125 MSPS operation, flexible CMOS/LVDS DDR output modes for FPGA/ASIC interface compatibility, internal bandgap reference with external override, and built-in input common-mode adjustment for transformer-coupled or single-ended drive. The 40-HVQFN package with exposed pad (SOT618-1 / MO-220) gives thermal resistance low enough to handle typical dissipation without external heatsinking.
Typical applications are high-density medical imaging front ends, cable DOCSIS edge digitizers, wireless IF baseband receivers, and radar/sonar pre-processing channels. The pipelined latency and DDR outputs are well-suited to FPGA-based digital downconversion.
When designing with this part, route analog inputs as 50 ohm differential microstrip with controlled impedance, place the decoupling capacitors within 2 mm of the supply pins, and follow the datasheet layout guidance for the exposed pad (EP) thermal connection to a continuous ground plane.
Drop-in alternatives for ADC1210S125HN/C1:5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1210S125HN/C1:5 (same form factor and footprint) — differing in Package, Resolution, Operating Temperature, Digital Output Interface, Input Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1015S125HN/C1
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$10.4 / Unit
View Datasheet →ADC1010S125HN/C1:5
✅ Drop-In✓ In Stock
$22.1 / Unit
View Datasheet →ADC1210S065HN/C1
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →ADC1010S105HN/C1:5
✅ Drop-In✓ In Stock
$9.62 / Unit
View Datasheet →ADC1012D080HN/C1:5
✅ Drop-In✓ In Stock
$12.1 / Unit
View Datasheet →ADC1210S125HN/C1:5 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Number of Channels | 1 |
| Sample Rate | 125 MSPS |
| Input Type | Differential, Single-Ended |
| Data Interface | CMOS / LVDS DDR |
| Architecture | Pipelined |
| Package | HVQFN-40 (6x6 mm) SOT618-1, MO-220 |
| Package Height | 0.85 mm |
| Operating Temperature | -40C to +85C |
| Screening Level | Industrial |
| Number of Pins | 40 |
| Mounting Type | Surface Mount |
| Reference Type | Internal / External |
| RoHS Status | Compliant |
| Lead-Free | Yes |
ADC1210S125HN/C1:5 Pin Configuration
| Pin 1 | AVDD — Analog supply voltage |
| Pin 2 | VIN+ — Differential analog input positive |
| Pin 3 | VIN- — Differential analog input negative |
| Pin 4 | VCM — Common-mode voltage output |
| Pin 5 | REFT — Top reference decoupling |
| Pin 6 | REFB — Bottom reference decoupling |
| Pin 7 | VREF — Reference voltage I/O |
| Pin 8 | AGND — Analog ground |
| Pin 9 | CLK+ — Differential clock input positive |
| Pin 10 | CLK- — Differential clock input negative |
| Pin 11 | DRVDD — Digital output supply |
| Pin 12 | DRGND — Digital ground |
| Pin 13 | D0_0 — LVDS/CMOS data output bit 0 (LSB lane 0) |
| Pin 14 | D0_1 — LVDS/CMOS data output bit 1 (lane 0) |
| Pin 15 | D0_2 — LVDS/CMOS data output bit 2 (lane 0) |
| Pin 16 | D0_3 — LVDS/CMOS data output bit 3 (lane 0) |
| Pin 17 | D0_4 — LVDS/CMOS data output bit 4 (lane 0) |
| Pin 18 | D0_5 — LVDS/CMOS data output bit 5 (lane 0) |
| Pin 19 | D0_6 — LVDS/CMOS data output bit 6 (lane 0) |
| Pin 20 | D0_7 — LVDS/CMOS data output bit 7 (lane 0) |
| Pin 21 | D0_8 — LVDS/CMOS data output bit 8 (lane 0) |
| Pin 22 | D0_9 — LVDS/CMOS data output bit 9 (lane 0) |
| Pin 23 | D0_10 — LVDS/CMOS data output bit 10 (lane 0) |
| Pin 24 | D0_11 — LVDS/CMOS data output bit 11 (MSB lane 0) |
| Pin 25 | DCLK — LVDS/CMOS data clock output |
| Pin 26 | DRGND — Digital ground |
| Pin 27 | DRVDD — Digital output supply |
| Pin 28 | OGND — Output driver ground |
| Pin 29 | OVDD — Output driver supply |
| Pin 30 | CS — Chip select / serial interface enable |
| Pin 31 | SCLK — Serial interface clock |
| Pin 32 | SDIO — Serial interface data I/O |
| Pin 33 | SDO — Serial interface data output |
| Pin 34 | RESET — Active-low chip reset |
| Pin 35 | PD — Active-low power down |
| Pin 36 | MODE — Output mode select (CMOS / LVDS DDR) |
| Pin 37 | AVDD — Analog supply voltage |
| Pin 38 | AVDD — Analog supply voltage |
| Pin 39 | AGND — Analog ground |
| Pin 40 | AGND — Analog ground |
Typical Applications
ADC1210S125HN/C1:5 is suitable for 6 applications: Medical Imaging (Ultrasound / OCT), Cable / Broadband DOCSIS Edge Digitizer, Wireless IF Baseband Receiver, Radar / Sonar Pre-Processing, Industrial Test & Measurement Instrumentation, Imaging / Video Broadcast Processing.
Medical Imaging (Ultrasound / OCT)
The ADC1210S125HN/C1:5 fits ultrasound beamformer and OCT receiver front ends because its 12-bit resolution and 125 MSPS sample rate give adequate dynamic range for mid-tier imaging channels. The differential analog input accepts transformer-coupled transducer drive with the datasheet-recommended input network, while the LVDS DDR output mode streams samples directly into an FPGA-based beamforming pipeline. Compared to lower-speed medical ADCs (40-65 MSPS), the 125 MSPS rate captures wider IF bandwidth and supports harmonic imaging without aliasing. The 40-HVQFN exposed pad provides thermal headroom for the dense channel counts typical of phased-array ultrasound probes.
Recommended
Cable / Broadband DOCSIS Edge Digitizer
Cable edge QAM/DOCSIS receivers demand 100+ MSPS ADCs with strong SFDR to capture multi-MHz channel bands without aliasing. The ADC1210S125HN/C1:5's 125 MSPS rate comfortably samples the upstream cable spectrum at baseband, and its LVDS DDR outputs route cleanly to DOCSIS MAC/FPGA processors over controlled-impedance differential traces. The selectable CMOS mode simplifies designs targeting lower-cost ASIC MACs. Compared to integrated tuner solutions, a discrete ADC1210S125HN/C1:5 + FPGA chain gives designers flexibility to tune anti-alias filtering and channelization for evolving DOCSIS 3.1 / 4.0 requirements.
Recommended
Wireless IF Baseband Receiver
The ADC1210S125HN/C1:5 suits wireless IF baseband digitizers in software-defined radio (SDR) and small-cell base station receivers, where 12-bit / 125 MSPS captures IF bandwidths of 30-60 MHz with sufficient dynamic range. The differential analog input accepts direct IF sampling from the mixer output, removing the need for a final downconversion stage in many architectures. Its LVDS DDR outputs feed FPGAs implementing DDC (digital downconversion), CIC filtering, and channelization. Compared to 14-16 bit parts at this speed, the 12-bit ADC trades dynamic range for lower power - appropriate for non-AFE critical SDR chains.
Recommended
Radar / Sonar Pre-Processing
Radar IF digitizers and sonar beamforming channels benefit from the ADC1210S125HN/C1:5's combination of 12-bit resolution, 125 MSPS rate, and pipelined deterministic latency. Pipelined ADCs introduce a fixed clock-cycle latency that simplifies multi-channel phase alignment - critical for phased-array beamforming. The LVDS DDR outputs maintain timing integrity over the backplane distances typical of sonar arrays. Compared to lower-rate SAR ADCs, the pipelined architecture avoids per-sample conversion overhead and supports continuous streaming at full bandwidth without throughput gaps.
Recommended
Industrial Test & Measurement Instrumentation
Test and measurement digitizer cards (oscilloscope channels, spectrum analyzer IFs, data-acquisition boards) commonly use 12-bit 100-125 MSPS ADCs like the ADC1210S125HN/C1:5 for accurate waveform capture at MHz bandwidths. The selectable CMOS or LVDS DDR output mode lets designers route signals to FPGAs or to backplane connectors for multi-channel synchronization. The exposed-pad HVQFN package improves thermal performance when digitizer channels are densely populated. Compared to higher-resolution (16-bit) ADCs at the same speed, the 12-bit ADC1210S125HN/C1:5 offers lower cost and lower power while still meeting typical mid-tier instrument accuracy requirements.
Recommended
Imaging / Video Broadcast Processing
Professional video broadcast and image processing systems use 12-bit ADCs at 100+ MSPS for component video digitizing, video capture cards, and broadcast signal processing. The ADC1210S125HN/C1:5's selectable CMOS outputs and LVDS DDR mode give flexibility to interface directly to broadcast ASICs or high-speed FPGAs handling real-time video pipelines. The differential input rejects common-mode noise from long cable runs typical in broadcast environments. Compared to dedicated video ADCs with embedded clamping, the ADC1210S125HN/C1:5 requires external input conditioning but provides wider sample-rate flexibility for non-standard video formats.
Recommended
Recommended Products Summary
Engineering reference data for ADC1210S125HN/C1:5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1015S125HN/C1 | ADC1010S125HN/C1:5 | ADC1210S065HN/C1 | ADC1010S105HN/C1:5 | ADC1012D080HN/C1:5 |
|---|---|---|---|---|---|---|
| Package | HVQFN-40 (6x6 mm) | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Resolution | 12 bit | 10 bit | 10 bit | 12 bit | 10 bit | 10 bit |
| Sample Rate | 125 MSPS | 125 MSPS | 125 MSPS | 65 MSPS | 105 MSPS | 80 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 2 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Output Interface | CMOS / LVDS DDR | CMOS / LVDS DDR | CMOS / LVDS DDR | CMOS / LVDS DDR | CMOS / LVDS DDR | CMOS / LVDS DDR |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Selectable CMOS / LVDS DDR outputs (vs ADC1210S065HN/C1)
- 12-bit resolution at 125 MSPS (vs ADC1015S125HN/C1)
- Single 12-bit channel at full speed (vs ADC1012D080HN/C1:5)
Design Notes
Route analog inputs (VIN+/VIN-) and clock inputs (CLK+/CLK-) as 50 ohm controlled-impedance differential microstrip pairs with reference plane on the layer immediately below. Place input common-mode network within 5 mm of the input pins and isolate the analog section from the digital output section with a continuous ground moat - this prevents digital switching noise from coupling into the sensitive analog front end.
Decouple AVDD and DRVDD supplies with separate ferrite beads or filter inductors, then place a 0.1 uF ceramic capacitor within 2 mm of each supply pin plus a 10 uF bulk capacitor per supply rail. Avoid sharing analog and digital supply planes - the ADC1210S125HN/C1:5 datasheet specifies independent AVDD/DRVDD/OVDD pins precisely to prevent digital switching transients from modulating the analog front end and degrading SFDR.
The HVQFN-40 exposed pad (EP) is the primary thermal dissipation path - solder it to a continuous ground plane with thermal vias (5x5 array of 0.3 mm vias recommended) connecting to inner ground layers. Without proper EP soldering, junction temperature can rise 20-30C above expected at 125 MSPS operation, degrading long-term reliability. Estimated: at typical 1.0W dissipation and JEDEC EIA/JESD51 test board, theta_JA is ~30 C/W.
Clock jitter directly limits achievable SNR at high input frequencies - use a low-jitter clock source (jitter < 1 ps rms) and route the clock traces symmetrically with matched length for CLK+/CLK-. The LVDS DDR mode doubles the per-pin data rate; ensure the FPGA receiver supports the resulting 250 Mbps DDR rate per data lane. Do not exceed the maximum AVDD supply voltage rating or omit the VCM decoupling capacitor (10 uF ceramic).
Compliance Information
RoHS and lead-free compliance stated on distributor listings. AEC-Q100 automotive qualification not available for this industrial-grade part; no -Q1 automotive variant listed by NXP. REACH and halogen-free status not explicitly stated in verified web data.
