ADC/DAC
Products (2518)
AS1544-BQFT - 12-Bit 1MSPS 4-Ch SAR ADC | ams OSRAM
The ams OSRAM AS1544-BQFT is a 12-bit, 1 MSPS, low-power, 4-channel (2 differential) successive-approximation analog-to-digital converter (SAR ADC) housed in a 20-pin TQFN (4x4) package with exposed thermal pad. Operating from a single 2.7 V to 5.25 V supply, the device delivers high throughput with low power consumption, making it well suited for battery-powered and multi-channel data-acquisition systems. A successive-approximation register (SAR) ADC is a type of data converter that performs a binary search across an internal capacitive DAC to resolve the input voltage one bit at a time per clock cycle. SAR ADCs sit within the broader data-converter IC family (SAR -> ADC -> data converter -> mixed-signal IC) and are favored for applications requiring deterministic latency, single-shot accuracy, and excellent dynamic performance without the complexity of pipeline or delta-sigma architectures. Key specifications of the AS1544-BQFT include a 1 MSPS sampling rate, 4 single-ended or 2 fully differential analog inputs, an integrated channel sequencer for automatic sequential conversions, and an SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface. A wide 2.7 V to 5.25 V analog supply range allows direct interfacing to 3.3 V and 5 V system rails. The 20-pin TQFN-EP (4x4 mm) package provides a small footprint suitable for space-constrained PCB designs while the exposed pad enhances thermal dissipation. The device architecture uses a sample-and-hold front end feeding a precision capacitive DAC and comparator, with conversion timing controlled by the external serial clock (SCLK) which also acts as the master conversion clock. The single-supply operation and channel sequencer eliminate the need for an external multiplexer in multi-channel monitoring applications, reducing both BOM count and software complexity. Typical applications include portable instrumentation, multi-channel sensor monitoring, industrial process control, automotive sensor interface, and battery management systems. The integrated sequencer makes the part especially attractive for cyclic channel-scanning designs where deterministic channel-to-channel timing is required. When designing with the AS1544-BQFT, ensure the SCLK frequency is held within the converter's specified range to maintain 1 MSPS throughput, place decoupling capacitors close to AVDD and DVDD pins, and connect the exposed pad to a clean analog ground plane for optimal thermal and noise performance. This page synthesizes distributor pricing, same-family cross references, and practical design notes not found in the manufacturer datasheet alone.
AS1545 - Dual 12-bit 1MSPS 6-ch SAR ADC | ams OSRAM
The ams OSRAM AS1545 is a dual, 12-bit, 6-channel, 1 MSPS, successive-approximation-register (SAR) analog-to-digital converter in a 32-pin TQFN (5x5 mm) package with exposed thermal pad. According to the ams OSRAM datasheet, the device operates from a single +2.7 V to +5.25 V supply, integrates two synchronized SAR ADCs each preceded by a 6-channel input multiplexer and a high-bandwidth track-and-hold amplifier, and offers a serial data interface for compact microcontroller or DSP readback. What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a precision data-conversion architecture that performs one bit at a time using a comparator, a digital-to-analog converter and a binary-search register, achieving 12 to 18 effective bits with no pipeline latency. SAR ADCs sit at the midpoint of the converter hierarchy between flash ADCs (fastest, lowest resolution) and sigma-delta ADCs (highest resolution, lowest bandwidth), and they remain the dominant choice for multiplexed multi-channel data acquisition at 100 kSPS to several MSPS where both speed and DC accuracy matter. Key specifications include 12-bit resolution, 1 MSPS sampling rate per channel, six single-ended analog inputs per ADC (twelve total), single-supply +2.7 V to +5.25 V operation, -40 C to +85 C operating temperature range, and a serial digital interface. The two integrated 6:1 multiplexers double the effective channel count without an external analog switch, while the on-chip track-and-hold supports full-scale step inputs at 1 MSPS without distortion. The architecture uses two simultaneous sampling SAR cores sharing an internal clock generator, a precision bandgap reference buffer, and a unified serial data port. This dual-core topology lets designers acquire two independent signal groups (such as voltage and current on a polyphase power stage) at the same instant, avoiding the time skew that two cascaded ADCs would introduce. Typical applications include industrial process control and PLC analog front ends, multi-phase power-supply voltage and current monitoring, motor-control feedback sensing, medical instrumentation signal acquisition, and portable data loggers or battery-powered sensor hubs. The wide 2.7 V to 5.25 V supply range lets a single part run directly from a 3.3 V MCU rail or a 5 V analog rail. When designing with this part, route the analog and digital grounds as separate islands tied at a single star point under the exposed pad, and place the supply bypass network (10 uF bulk plus 100 nF X7R) within 3 mm of the AVDD and DVDD pins. The exposed thermal pad must be soldered to a continuous ground plane to keep junction temperature within the -40 C to +85 C operating envelope. This page synthesizes ams OSRAM datasheet specifications, distributor pricing, drop-in alternatives in the same 32-TQFN footprint, and practical PCB layout notes not collated in the manufacturer's datasheet alone.
AS89020 - 4-Ch 12-bit Current-Input ADC | ams OSRAM
The ams OSRAM AS89020 is a 4-channel, 12-bit successive approximation register (SAR) analog-to-digital converter with current-mode inputs, packaged in a 20-pin SSOP. Each channel is independently addressable and programmable in 17 sensitivity levels, with a finest sensitivity of approximately 2.8 pA/LSB, making the device well suited to direct readout of photodiodes (e.g. RGB or XYZ color sensors) and other current-output transducers without external transimpedance stages. An ADC of this current-input type belongs to the data-converter family of mixed-signal integrated circuits. The SAR architecture performs a binary search through an internal capacitive DAC each conversion cycle, settling in one clock rather than integrating over many cycles, which preserves input bandwidth and rejects 50 Hz/60 Hz line-frequency noise only with additional filtering. In the broader system taxonomy, the AS89020 sits inside signal-chain ICs -> data converters -> analog-to-digital converters -> precision SAR ADCs -> photo-sensor front-ends. Key features highlighted by the manufacturer datasheet include on-chip temperature compensation, measurement support for both positive and negative input currents (bidirectional), and a fast SPI-compatible serial digital interface for read-out and channel programming. The 17 programmable gain/sensitivity levels per channel allow the application firmware to re-scale the full-scale range as light levels change, which simplifies dynamic-range management in color-sensing applications. The analog front-end integrates low-noise current integrators and a temperature-compensated bandgap reference, removing the need for an external reference IC and reducing BOM count. Because each channel includes its own integrator, the four photodiodes can be read independently and at different integration times, which is useful when matching a red-, green-, blue-, and clear-channel response of a colorimeter. Typical end applications are ambient-light and color-sensing modules, XYZ tristimulus colorimeters, RGB LED feedback loops, industrial photo-interpreters, and handheld colorimeters. The on-chip temperature compensation also allows the part to be used in closed-loop luminous-intensity control where photodiode drift over temperature must be cancelled in firmware. When designing with this part, choose the per-channel integration time and sensitivity setting to keep the photodiode output current well within the programmed full-scale range; over-range currents can saturate the integrator and clip the conversion. Decouple VDD with a low-ESR 100 nF ceramic capacitor placed within a few millimetres of the supply pin to preserve converter linearity. This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a faster path from part selection to prototype build.
CDK1307AILP40 - 12/13-bit 20MSPS Ultra-Low Power ADC | MaxLinear
The MaxLinear CDK1307AILP40 is a 12/13-bit, 20MSPS ultra-low-power analog-to-digital converter (ADC) housed in a 40-pin QFN package. The part is part of the CDK1307A family, which supports 12/13-bit resolution and sampling rates of 20/40/65/80MSPS, with 19mW power dissipation at maximum throughput and 72.6 dB SNR at 8MHz analog input. An analog-to-digital converter (ADC) is an integrated circuit that converts continuous analog signals into discrete digital codes. The ADC is a critical bridge in the signal chain between the analog front end (sensors, amplifiers, filters) and the digital processing domain (DSP, microcontrollers, FPGAs). Within the broader IC taxonomy, ADCs belong to data converters -> mixed-signal ICs -> semiconductor. The CDK1307A family targets high-performance, low-power applications where SNR, throughput, and power budget must all be optimized simultaneously. Key features include 12/13-bit resolution, 20MSPS maximum sampling rate, 19mW ultra-low power dissipation, 72.6 dB SNR at 8MHz analog input, internal reference circuitry, 1.8V core supply, 1.7V to 3.6V I/O supply, and parallel CMOS output interface. The 40-pin QFN package is pin-compatible with the CDK1308 family, simplifying board-level migration between speed grades. The CDK1307A utilizes a pipelined architecture with digital error correction, allowing the device to maintain high SNR performance at high input frequencies. Internal reference circuitry eliminates the need for external reference components, reducing BOM cost and board area while maintaining low drift over temperature. Typical applications include portable and battery-powered imaging systems, portable test and measurement equipment, hand-held oscilloscopes, ultrasound front-end digitization, and low-power digital communications receivers. The 20MSPS throughput makes it well suited to IF sampling and baseband conversion in software-defined radio. When designing with this device, ensure the analog input network (driver amplifier and RC network) is configured to match the ADC's input common-mode and bandwidth. The 1.8V core supply and 1.7-3.6V I/O supply allow direct interfacing to modern low-voltage FPGAs and processors without level shifters. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
CDK1307BILP40 - 13-bit 40MSPS Ultra-Low Power ADC | MaxLinear
The MaxLinear CDK1307BILP40 is an ultra-low-power, 13-bit (configurable to 12-bit) analog-to-digital converter supporting sampling rates from 1 to 40 MSPS, housed in a 40-pin QFN (6x6 mm, ILP40 suffix) package. The part is pin-compatible with the higher-speed CDK1308 family member, allowing designers to drop it onto existing layouts where a 40 MSPS ceiling is adequate. An ADC (analog-to-digital converter) is a data-acquisition component that samples continuous analog signals and outputs discrete digital codes at a sample rate set by an external clock. ADCs sit at the boundary between the analog front end (sensors, amplifiers, filters) and the digital processing block (DSP, FPGA, microcontroller), and are characterized by resolution (bits), sample rate (MSPS), SNR/SFDR dynamic performance, input bandwidth, and power dissipation. Ultra-low-power ADCs such as the CDK1307 family target portable, battery-powered, and thermally constrained systems where every milliwatt matters. Key features include a 1.8 V analog core supply, a 1.7 V to 3.6 V digital I/O supply for direct host-MCU interfacing, internal reference circuitry to minimize external component count, and parallel CMOS output that simplifies PCB routing compared with LVDS interfaces. The 73 dB SNR (typical at 8 MHz input) and 33 mW typical dissipation position this part for low-power imaging, instrumentation, and communications receiver applications where thermal management is a design constraint. Architecturally the CDK1307BILP40 uses a successive-approximation or pipelined core (per the CDK1307 family datasheet) with on-chip sample-and-hold and an internal reference. The wide I/O voltage range (1.7-3.6 V) allows direct connection to 1.8 V, 2.5 V, and 3.3 V MCUs or FPGAs without level shifters, simplifying BOM and reducing board area in multi-rail designs. Typical applications include portable ultrasound front-ends, handheld instrumentation, low-power wireless baseband receivers, industrial sensor digitizers, and consumer imaging pipelines. The 40 MSPS ceiling is well-matched to narrowband IF sampling in software-defined radio and to video-rate processing at reduced resolutions. When designing with the CDK1307BILP40, treat the analog and digital supplies as separate rails and place the decoupling network within 5 mm of the supply pins. The internal reference eliminates the need for an external reference IC in most designs, but PCB layout must still follow good ADC practice: a solid analog ground plane, short analog input traces, and the digital outputs routed away from the analog input to avoid digital-feedback coupling. This page synthesizes distributor inventory, parametric position within the CDK1307 family, application mapping, and practical PCB-layout guidance that goes beyond the bare specification tables published on individual distributor pages.
CDK1307CILP40 - 12/13-bit 65MSPS Ultra-Low Power ADC | Exar
The Exar (formerly Cadeka) CDK1307CILP40 is an ultra-low-power, 12/13-bit analog-to-digital converter (ADC) supporting sample rates of 20/40/65/80 MSPS, housed in a 40-pin LQFP (LP) package. The 65 MSPS speed grade is selected by the device suffix; the family shares a common CMOS control interface, CMOS-compatible output data, internal reference, and proprietary multi-stage pipeline architecture with digital error correction. An analog-to-digital converter (ADC) is a data-conversion integrated circuit that samples continuous analog input signals and converts them into discrete digital codes for downstream digital signal processing. The CDK1307 sits inside the data-converter -> signal-chain -> mixed-signal IC hierarchy and is typically paired with a low-noise operational amplifier front-end and a downstream FPGA, DSP, or microcontroller. The "CILP40" suffix encodes both the temperature grade (-40 C to +85 C industrial range) and the 40-pin LQFP package. Key features per the manufacturer datasheet include a single 3.3 V analog supply, internal 1.2 V reference, CMOS digital outputs, low standby current of 9 mW typical at 65 MSPS, and an external clock input with duty-cycle stabilizer. The converter accepts single-ended analog inputs typically centered at 1.5 V with a 1 Vpp full-scale range, and provides 12-bit or 13-bit selectable resolution through the configuration register. Architecturally, the CDK1307CILP40 uses a multi-stage pipelined switched-capacitor core with proprietary digital error correction. This pipeline topology enables high sample rates (up to 80 MSPS) at low power consumption by distributing the conversion work across cascaded stages. The internal bandgap-based reference and integrated clock-receiver circuitry minimize external component count. Typical applications include portable ultrasound front-ends, handheld industrial instrumentation, low-power imaging pipelines, IF/baseband digitizing for software-defined radio, and battery-powered test equipment. Designers also use the CDK1307 in medical patient-monitoring subsystems and portable oscilloscope front-ends where power budget is critical. Design tip: route the analog and digital grounds as separate nets that join only at the EP/exposed-pad or at the AGND/DGND pin per the datasheet layout example. Place input coupling capacitors close to the AIN pin and bypass AVDD/DVDD with 0.1 uF ceramic + 10 uF tantalum pairs. Maintain a stable low-jitter clock at ENC+/ENC- to avoid degrading SNR. This page synthesizes distributor stock data, drop-in alternatives, and practical layout guidance not collected in a single place in the manufacturer datasheet.
CDK1307DILP40 - 13-bit 80MSPS 60mW Ultra-Low Power ADC | MaxLinear
The MaxLinear (formerly Cadeka) CDK1307DILP40 is an ultra-low-power, 13-bit resolution analog-to-digital converter (ADC) that samples at up to 80 MSPS while consuming only 60 mW, packaged in a 40-pin QFN. The CDK1307DILP40 is the 80 MSPS speed grade (suffix D) in the CDK1307 ADC family and is pin-compatible with the higher-resolution CDK1308 sibling device, allowing system designers to migrate between 12-bit, 13-bit and 14-bit resolutions on the same PCB land pattern. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time, continuous-amplitude analog signals into discrete-time, discrete-amplitude digital codes. The CDK1307 family belongs to the pipeline ADC category, which uses a multi-stage switched-capacitor architecture to deliver high sample rates at moderate resolution. Within the broader IC hierarchy, an ADC sits under data converters, which themselves are a sub-category of data acquisition ICs and ultimately signal conditioning semiconductors used in virtually every electronic system that bridges the analog physical world with digital processors. Key features highlighted in the verified data include a 72.4 dB SNR at an analog input frequency of 8 MHz, internal reference circuitry that eliminates the need for an external voltage reference, a 1.8 V core supply voltage, and a wide 1.7 V to 3.6 V I/O supply range that interfaces directly to 1.8 V, 2.5 V, and 3.3 V logic. The differential clock interface is optimized for low jitter, and a highly linear track-and-hold amplifier (THA) preserves dynamic performance at input frequencies up to the Nyquist limit. Two idle modes - Standby and Power Down - provide fast wake-up with minimized quiescent energy, which is critical for battery-powered or duty-cycled systems. The pipeline architecture uses successive low-resolution stages with digital error correction, achieving 13-bit linearity without laser trimming. Parallel CMOS outputs simplify the digital interface to FPGAs, ASICs, or microcontrollers without requiring an external serializer. The combination of high SNR, low power dissipation, and a small 40-pin QFN footprint makes the CDK1307DILP40 suitable for portable instrumentation where every milliwatt and every square millimeter matter. Typical applications include medical imaging front ends, portable test equipment, digital oscilloscopes, IF-sampling communications receivers, and handheld industrial sensors. The wide I/O voltage range also simplifies interfacing to modern low-voltage FPGAs without level shifters. When designing with this part, ensure the analog input network presents a differential drive to achieve the rated 72.4 dB SNR. Decouple the 1.8 V analog supply and the I/O supply separately near the IC pins, and provide a clean low-jitter clock through the differential CLK+/CLK- pins to maximize spurious-free dynamic range. This page consolidates distributor pricing, parametric data, and drop-in-compatible alternatives for the CDK1307DILP40, providing practical engineering context beyond the raw manufacturer datasheet.
CDK1308AILP40 - 10-bit 20MSPS Ultra-Low-Power ADC | MaxLinear
The MaxLinear CDK1308AILP40 is a 10-bit, 20 MSPS ultra-low-power analog-to-digital converter (ADC) housed in a 40-pin QFN package. According to the manufacturer datasheet, the device features internal reference circuitry, a CMOS control interface, CMOS output data, and digital error correction. It is part of the CDK1308 family which scales sample rate across 20/40/65/80 MSPS variants, allowing system designers to select the bandwidth that matches their signal chain. As of 2026-10-13, the part is in production and available through authorized distributors including Mouser, Octopart-listed stockists, and MaxLinear franchised partners. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time, continuous-amplitude analog signals into discrete-time, discrete-amplitude digital codes. The CDK1308 family sits in the precision data-converter category, a sub-family of signal-chain data acquisition ICs that bridge analog sensors and digital processors. Within the broader IC hierarchy: ADC -> data converter -> data acquisition IC -> mixed-signal IC -> semiconductor. Successive-approximation (SAR) and pipelined architectures dominate the 1-80 MSPS tier where the CDK1308 competes, with power consumption, channel count, and SNR/ENOB being the primary differentiators. Key features of the CDK1308AILP40 include a 20 MSPS maximum sampling rate, 10-bit resolution, ultra-low power consumption relative to competing 10-bit ADCs at the same throughput, single-supply operation, CMOS-compatible digital outputs, and a parallel data interface. The device employs digital error correction to mitigate pipeline-stage linearity errors, and a proprietary internal reference that eliminates the need for an external reference IC in most designs. The combination of internal reference, small QFN package, and low quiescent power makes the part attractive for portable, space-constrained designs. Typical applications for the CDK1308AILP40 include portable test and measurement equipment, USB oscilloscope front ends, medical imaging signal conditioning, and mid-bandwidth industrial instrumentation. Designers choose this part when 10-bit resolution is sufficient and the primary design constraint is power budget rather than absolute noise performance. Compared with 12/14-bit alternatives, the 10-bit architecture trades dynamic range for substantially lower power and smaller die area, which translates directly into battery run-time and PCB footprint. When designing with the CDK1308AILP40, route the analog inputs with guarded differential pairs and decouple AVDD/DRVDD with separate 1uF and 0.1uF ceramic capacitors placed as close as possible to the supply pins. The PD_N (power-down) and SLP_N (sleep) pins can be used for duty-cycled operation in battery-powered designs. Drive the analog input with a low-impedance, low-noise op-amp front end, and ensure the clock source is a low-jitter LVCMOS or LVPECL driver to avoid degrading SNR. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet. Specifications are referenced to the MaxLinear CDK1308 datasheet family; consult the manufacturer document for absolute maximum ratings and characterization curves.
CDK1308BILP40 - 10-bit 40MSPS Ultra-Low Power ADC | MaxLinear
The MaxLinear (formerly Exar Corporation) CDK1308BILP40 is a 10-bit, 40 MSPS ultra-low-power analog-to-digital converter (ADC) housed in a 40-pin QFN package (LP40). The CDK1308 family is offered in four speed grades (20/40/65/80 MSPS), and the BILP40 suffix denotes the 40 MSPS speed grade with industrial temperature range. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time, continuous-amplitude analog signals into discrete digital codes. Within the broader signal chain hierarchy, ADCs sit between analog front-end conditioning (amplifiers, anti-alias filters) and digital processing (FPGA, microcontroller, DSP), making them a critical component in data acquisition systems, imaging, and communications equipment. Ultra-low-power ADCs such as the CDK1308 target portable and battery-powered applications where milliwatts-per-sample directly impact battery life and thermal budgets. Key features include 25 mW typical power dissipation at 40 MSPS, 61.6 dB SNR at an 8 MHz analog input, internal reference circuitry (eliminating external reference components), a 1.8 V analog core supply, and a separate 1.7 V to 3.6 V digital I/O supply for flexible host interfacing. The device uses a proprietary CMOS architecture with digital error correction, delivering high linearity while keeping die area and power low. Parallel CMOS outputs simplify connection to FPGAs, ASICs, and microcontrollers without requiring an external serializer. The CDK1308B is pin-compatible with the CDK1307 family, enabling system scalability between 10-bit (CDK1308) and 12-bit (CDK1307) resolutions on the same PCB. This makes the part attractive for medical imaging, portable test equipment, digital oscilloscopes, and IF communications designs where a single hardware platform must support multiple performance tiers. Typical applications span handheld ultrasound front-ends, digital oscilloscopes, IF sampling for software-defined radio (SDR), and portable industrial inspection cameras. The combination of low power, small QFN footprint, and internal reference simplifies multi-channel designs where board area and BOM cost are constrained. When designing with the CDK1308BILP40, decouple AVDD and DVDD separately with 1 µF and 100 nF capacitors placed as close to the pins as possible. Drive the analog input through a wideband op-amp or transformer; the input is a switched-capacitor structure that benefits from a low-impedance source to preserve SNR at high input frequencies.
CDK1308CILP40 - 10-bit 40MSPS Ultra-Low-Power ADC | MaxLinear
The MaxLinear CDK1308CILP40 is a 10-bit resolution, 40 MSPS sampling-rate, ultra-low-power analog-to-digital converter (ADC) housed in a 40-pin LQFP package. As a member of the CDK1308 family (20/40/65/80 MSPS variants), it is engineered for low-power portable applications where high dynamic range and small footprint are required. According to the MaxLinear datasheet (Rev 1B), the CDK1308C dissipates only 38 mW at 65 MSPS, making it one of the lowest-power 10-bit pipeline ADCs in its speed class. An analog-to-digital converter (ADC) is a semiconductor device that converts real-world continuous analog signals into discrete digital codes for processing by microcontrollers, FPGAs, or DSPs. Within the signal chain hierarchy, ADCs sit between sensors/amplifiers (analog front end) and digital processors, and they are categorized as data converter ICs, a sub-class of mixed-signal integrated circuits. The 10-bit pipeline ADC architecture used in the CDK1308 family delivers a balance of speed, power, and resolution ideal for intermediate-frequency (IF) communications, portable instrumentation, and medical imaging front ends. Key features of the CDK1308CILP40 include 61.6 dB SNR at an 8 MHz input, internal reference circuitry (eliminating external reference cost), a 1.8 V analog core supply, and a 1.7 V to 3.6 V digital I/O supply that interfaces directly to 1.8 V, 2.5 V, or 3.3 V logic families. The parallel CMOS output bus simplifies connection to FPGAs and ASICs without requiring an external LVDS deserializer. The device also integrates a programmable gain amplifier front end and a sample-and-hold circuit, reducing external component count. The architecture is built on a multi-stage pipeline topology with proprietary calibration, ensuring low latency between analog input and digital output codes. Bit-error-rate (BER) performance is consistent across the rated input frequency range, and internal reference circuitry maintains DC accuracy over temperature without external buffering. Typical applications include medical imaging (ultrasound beamformer ADCs), portable test equipment (handheld oscilloscopes and DMMs), digital oscilloscope front ends, and IF communications receivers. Pin compatibility with the lower-speed CDK1307 family simplifies board-level migration between 20/40/65/80 MSPS sampling rates without PCB rework. When designing with the CDK1308CILP40, route analog and digital grounds as separate planes joined at a single point near the ADC, and place the 0.1 µF decoupling capacitors within 2 mm of each supply pin. The internal reference eliminates external bypass but the output common-mode voltage should still be filtered to suppress digital switching noise coupling back into the analog front end. This page synthesizes MaxLinear datasheet specifications, parametric alternatives, and practical design notes not found in the manufacturer datasheet alone.
CDK1308DILP40 - 10-bit 80MSPS Low-Power ADC | MaxLinear
The MaxLinear (formerly Exar) CDK1308DILP40 is a 10-bit resolution, 80 MSPS maximum sampling rate analog-to-digital converter (ADC) housed in a 40-pin QFN (6x6 mm) package. Its headline specifications are 4.17... wait, let me restate: the verified headliners are 80 MSPS sampling rate, 46 mW ultra-low power dissipation, 61.6 dB SNR at Fin = 8 MHz, and a 1.8 V core / 1.7-3.6 V I/O supply scheme. The L-suffix in CDK1308DI indicates industrial temperature range (-40C to +85C), and the LP40 package code denotes the 40-pin QFN. An ADC is a data-conversion integrated circuit that samples continuous analog signals and translates them into discrete digital codes for downstream microcontrollers, DSPs, or FPGAs. Pipeline ADCs like the CDK1308 family enable high-speed multi-MHz sampling with low power, occupying a middle position between low-speed SAR ADCs and very high-speed flash converters. The CDK1308DILP40 belongs to the broader data-acquisition and signal-chain semiconductor hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor device. Key features include a 10-bit parallel CMOS output interface, internal reference circuitry (eliminating external reference cost), a single 1.8 V analog supply rail plus a wide 1.7-3.6 V digital I/O supply for flexible host interfacing, and pin compatibility with the lower-speed CDK1307 family (40/65 MSPS) which allows one PCB layout to support multiple sampling-rate SKUs. Its 61.6 dB SNR is competitive for general-purpose imaging and baseband digitisation. Architecturally the CDK1308DILP40 uses a multi-stage pipeline core with proprietary error-correction logic and on-chip track-and-hold, allowing it to maintain low spurious content across the full Nyquist band without external calibration. The internal voltage reference simplifies design-in and reduces external BOM count. Typical applications include portable and handheld imaging systems, ultrasound front-end preprocessing, video digitisation, low-cost digital oscilloscopes, and industrial barcode/line-scan cameras where 80 MSPS and 10-bit resolution hit the application sweet spot. The wide 1.7-3.6 V digital I/O supply makes the part especially easy to interface with 1.8 V, 2.5 V, or 3.3 V FPGAs and processors without level shifters. When designing with this device, pay attention to the analog input common-mode voltage and provide a properly-decoupled analog AVDD rail; place the decoupling capacitors as close to the AVDD and DVDD pins as the layout allows to preserve the 61.6 dB SNR figure. This page aggregates distributor pricing, drop-in alternatives and practical layout notes - information not bundled together on any single manufacturer or distributor page.
CDK2307AILP64 - Dual 13-bit 20MSPS ADC | Cadeka | 64-QFN
The Cadeka (MaxLinear) CDK2307AILP64 is a dual-channel, 13-bit resolution, 20 MSPS analog-to-digital converter (ADC) housed in a 64-pin QFN (LP64) package. The device family supports user-selectable sampling rates of 20, 40, 65, or 80 MSPS across the CDK2307 family, with the 'A' speed grade designating the 20 MSPS variant. It features a single-ended analog input, parallel CMOS output, and operates from a 1.8V core supply and a 1.7V to 3.6V I/O supply. An analog-to-digital converter (ADC) is an integrated circuit that converts continuous analog voltage signals into discrete digital codes for processing by microcontrollers, DSPs, or FPGAs. Within the broader semiconductor hierarchy, ADCs are a sub-category of data conversion ICs, which themselves fall under signal conditioning and data acquisition. As a successive-approximation or pipelined sampling ADC (per Cadeka architecture), the CDK2307 family targets mid-speed applications where power efficiency and small footprint outweigh the need for >14-bit precision or >100 MSPS conversion rates. Key features include ultra-low power dissipation of 30 mW at 20 MSPS, an integrated bandgap reference and internal reference circuitry (eliminating the need for external reference components), digital error correction, and CMOS-compatible control and data interfaces. The 64-pin LP64 QFN package exposes a thermal pad that enables direct PCB heatsinking without external cooling hardware. Architecturally, the CDK2307 is built on a proprietary CMOS process with a pipelined or SAR-like core (per Cadeka datasheet), one internal reference per channel pair, and a shared digital error-correction block that calibrates comparator offset on-chip. The dual-channel simultaneous-sampling capability suits applications that require correlated I/Q or stereo capture. Typical applications include portable ultrasound front-ends, multi-channel data-acquisition boards, low-power medical imaging, communications IF/baseband digitizers, and handheld test instruments. Its low power budget also makes it suitable for battery-powered industrial sensors. When designing with this device, follow Cadeka's recommended analog-input RC network and provide clean, low-impedance ground returns to the exposed pad. The CDK2307 is pin-compatible with the CDK2308 family (12-bit variant), allowing system reuse across resolution tiers. This page synthesizes distributor pricing, drop-in and same-footprint alternatives, and practical design notes not found in the manufacturer datasheet.
CDK2307BILP64 - Dual 12/13-bit 40MSPS ADC | MaxLinear/Exar
The MaxLinear (formerly Exar/Cadeka) CDK2307BILP64 is a dual-channel, 12/13-bit pipelined analog-to-digital converter (ADC) sampling at up to 40 MSPS, housed in a 64-pin QFN-EP (9x9 mm) package. It integrates two independent ADC channels with internal reference circuitry, a CMOS control interface, and CMOS output data, delivering high performance for multi-channel data acquisition systems while keeping system power and footprint low. What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage switched-capacitor architecture that samples and quantizes analog input signals through cascaded low-resolution stages, with each stage driving the residue into the next. Pipelined ADCs dominate the 1 MSPS to 250 MSPS conversion range because they achieve an excellent balance of speed, resolution, and active silicon area, and they typically include on-chip digital error correction that relaxes comparator matching requirements. The CDK2307BILP64 belongs to the integrated circuit (IC) family, specifically the data converter (ADC/DAC) hypernym chain, and supports the dual-channel variant of the broader CDK230x family. Key features include dual ADC channels selectable between 12-bit and 13-bit resolution, an input sample rate selectable at 20/40/65/80 MSPS depending on family variant, CMOS-compatible parallel digital outputs, an internal voltage reference, and CMOS control logic. Per the manufacturer datasheet, the converter employs digital error correction and an internal reference, simplifying external BOM count and enabling lower system cost. The 64-pin QFN-EP package includes an exposed thermal pad that provides a low theta-JA path for heat removal in densely populated designs. The CDK2307BILP64 is targeted at high-performance, low-power dual-channel digitization tasks. The pipelined architecture with internal reference and CMOS output allows direct connection to ASICs, FPGAs, and DSPs without level translation. Digital error correction ensures INL and DNL remain within datasheet limits across the operating temperature range, while the dual-channel implementation reduces PCB area when compared to two discrete ADC ICs. Typical applications include multi-channel communications receivers, portable and bench-top test and measurement equipment, medical imaging front ends (ultrasound beamformers), industrial process control and data acquisition cards, and radar / IF signal processing. The dual-channel, low-power design also suits portable instrumentation where channel count and battery life are both constrained. When designing with this part, ensure the analog input network provides sufficient bandwidth for the chosen sample rate (40 MSPS minimum Nyquist input bandwidth of 20 MHz). Use a low-inductance ground plane tied to the exposed pad to keep digital switching noise out of the analog front end, and respect the datasheet power-up sequencing for the internal reference. This page synthesizes distributor pricing, parametric alternatives in the same QFN-EP footprint, and practical design notes not found in the manufacturer datasheet alone.
CDK2307CILP64 - Dual 65MSPS 12/13-bit ADC | MaxLinear
The MaxLinear (formerly Exar / Cadeka) CDK2307CILP64 is a dual-channel, 12/13-bit pipelined Analog-to-Digital Converter (ADC) capable of sampling at 20, 40, 65, or 80 MSPS per channel, housed in a 64-pin QFN (LP64) package with exposed thermal pad. The CDK2307 family provides high-performance, low-power dual ADC operation with internal reference circuitry, CMOS control interface and CMOS output data paths, based on a proprietary pipelined converter architecture with onboard digital error correction. An ADC (Analog-to-Digital Converter) is a data acquisition component that converts real-world analog signals into discrete digital codes for downstream processing by FPGAs, DSPs, microcontrollers, or ASICs. Within the converter hierarchy, the CDK2307CILP64 sits in the pipelined-ADC subcategory, which is the dominant topology for sampling rates between 10 MSPS and 250 MSPS because it balances high input bandwidth and resolution against modest die area and power. Selection between SAR (successive-approximation) and pipelined ADC families is driven primarily by the required sample rate and channel count. Key features include simultaneous dual-channel sampling at up to 80 MSPS, a maximum sample rate of 80 MSPS at 12 bits and 65 MSPS at 13 bits, CMOS-compatible digital I/O, and an internal voltage reference that eliminates external reference components. The wide input common-mode range and low differential nonlinearity (DNL) make the converter well-suited to intermediate-frequency (IF) sampling, multi-carrier base-station receivers, and high-density video / imaging front ends. Power dissipation scales linearly with sample rate, allowing designers to trade speed for power in lower-throughput operating modes. Architecturally, each channel of the CDK2307CILP64 uses a multi-stage pipelined switched-capacitor core followed by digital error-correction logic. The internal reference and clock-receiver blocks are shared between channels, while the analog inputs and digital outputs are independent, allowing simultaneous sampling of two real signals or one I/Q complex signal pair in a baseband or low-IF radio chain. Typical applications include wireless infrastructure (GSM/EDGE/UMTS base-station receiver IF stages), cable-modem / set-top box downstream digitizers, multi-channel test and measurement instruments, ultrasound beamforming front ends, and dual-channel imaging / video capture. The 64-pin QFN exposed-pad package supports surface-mount PCB assembly and provides a low-thermal-resistance path to the PCB copper for heat spreading during sustained high-sample-rate operation. When designing with this part, ensure each analog input is driven from a low-impedance, wideband differential buffer; bandwidth-limiting the analog front end below the Nyquist frequency (half the sample rate) prevents aliasing but must not degrade the aperture-time accuracy. Decouple AVDD and DVDD pins separately at the IC with 100 nF ceramic capacitors to keep the high-frequency switching currents out of the analog ground return. This page synthesizes distributor pricing, parametric comparisons against pin-compatible dual ADCs, and practical PCB-layout guidance that goes beyond what is found in the manufacturer datasheet PDF.
CDK2307DILP64 - Dual 13-bit 80MSPS ADC | Cadeka/MaxLinear QFN-64
The Cadeka (now MaxLinear) CDK2307DILP64 is a dual-channel, 12/13-bit pipelined Analog-to-Digital Converter sampling up to 80 MSPS per channel, housed in a 64-pin QFN package with exposed pad (DIL suffix indicating tray packaging). Each ADC channel integrates internal reference circuitry, CMOS control logic, and CMOS parallel output data, with digital error correction for low residual offset and gain error. Per the manufacturer datasheet, the device operates from a single 1.7 V to 3.6 V analog supply and a separate 1.7 V to 3.6 V digital supply, consuming approximately 102 mW per channel at 80 MSPS. An ADC (Analog-to-Digital Converter) is a data converter that samples continuous analog signals and produces discrete digital codes. Within the data-converter hierarchy, the CDK2307DILP64 sits in the pipelined-ADC subfamily, which is the dominant architecture for sample rates between 5 MSPS and 250 MSPS because it balances high sample rate, moderate resolution, and low power per conversion. Pipelined ADCs are widely used in communications, medical imaging, instrumentation, and defense systems where a multi-MHz analog front-end must be digitized with 10-14 bit effective resolution. Key features of the CDK2307DILP64 include user-selectable 12-bit or 13-bit resolution, four speed grades (20/40/65/80 MSPS) shared across the family, a single-ended analog input, parallel CMOS output bus, and an internal bandgap reference. The dual-channel integration saves board area versus two discrete ADCs while maintaining channel-to-channel matching for time-interleaved or I/Q demodulation architectures. The 64-pin QFN package exposes a thermal pad, supporting the ~200 mW total dissipation without requiring an external heatsink. The pipelined core uses a multi-stage switched-capacitor architecture with per-stage MDAC gain of 2 and digital error correction, yielding low DNL and INL. The internal reference simplifies BOM cost, while a separate REFIN pin allows the user to drive an external reference for gain calibration or ratio-metric measurements. The CMOS output bus reduces digital switching noise on the supply rails, easing layout in mixed-signal designs. Typical applications include communications I/Q baseband digitization, multi-channel data acquisition cards, medical ultrasound beamformers, handheld test instrumentation, and industrial inspection imaging. Its dual channels suit diversity receivers, simultaneous-sample vibration analysis, and any design where PCB area or channel-to-channel skew is critical. When designing with this part, place the analog and digital supplies on separate PCB planes joined at a single ferrite bead near the IC, and bypass each supply pin with a 100 nF X7R capacitor within 2 mm of the pad. Use the exposed pad as the primary thermal and ground return path; failing to solder it degrades electrical and thermal performance. This page synthesizes distributor pricing, drop-in alternatives, and practical layout notes not consolidated on the manufacturer datasheet, giving engineers a faster starting point for dual-channel 80 MSPS designs.
CDK2308AILP64 - Dual 10-bit 20MSPS ADC | Exar | QFN-64
The Exar (MaxLinear) CDK2308AILP64 is a dual-channel, 10-bit analog-to-digital converter supporting 20/40/65/80 MSPS sampling rates, supplied in a 64-pin QFN (LP) 9x9 mm package with exposed thermal pad. The part provides two simultaneously-sampling ADC channels designed for high-speed signal acquisition in video, imaging, communications, and instrumentation systems. The device operates from a single +3.3 V analog supply and a separate +3.3 V digital supply, offering flexible CMOS-compatible output timing and low differential non-linearity (DNL) suitable for video-grade digitization. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes, enabling downstream digital signal processing, storage, or transmission. The CDK2308 belongs to the pipelined-architecture ADC family, which balances high sampling speed with moderate resolution (10-bit), making it a workhorse part for video broadcast equipment, IF sampling in communications receivers, and industrial machine-vision front ends. In the broader taxonomy: ADC -> data converter -> mixed-signal IC -> semiconductor. Key features of the CDK2308AILP64 include a maximum sample rate of 80 MSPS (the ILP64 grade supports 20 MSPS operation per the suffix code), 10-bit resolution, dual simultaneous-sampling channels, CMOS/TTL-compatible digital outputs, internal bandgap reference, and an integrated input buffer. The wide input bandwidth allows direct IF sampling in communication designs and pixel-rate capture in camera link systems. The device's pipelined architecture stages multiple low-resolution flash sub-ADCs to achieve a 10-bit result per sample while maintaining throughput above tens of MSPS. Internal calibration and error correction suppress inter-stage residue errors to deliver integral non-linearity (INL) and DNL within +/-1 LSB typical, supporting broadcast-quality video and broadband IF signal chains where linearity directly drives system signal-to-noise ratio. Typical applications include HD/SD video digitization, professional camera front ends, communications IF/baseband sampling, industrial test and measurement instrumentation, medical imaging (ultrasound beamformers), and defense signal-intelligence receivers. The dual-channel architecture is particularly attractive for I/Q demodulation, dual-polarity analog front ends, and stereo or RGB video capture where channel-to-channel matching is critical. When designing with the CDK2308AILP64, ensure the analog and digital supplies are well-decoupled with separate ferrite beads and bulk capacitors, and route the analog inputs as 50-ohm controlled-impedance differential pairs to the IC. The exposed thermal pad (EP) must be soldered to a continuous ground plane to dissipate ~0.5 W of internal power and minimize thermal resistance. This page synthesizes real-time distributor pricing, drop-in alternative parts, and engineering design notes that complement the Exar datasheet content.
CDK2308BILP64 - Dual 10-bit 40MSPS ADC | MaxLinear (Cadeka)
The MaxLinear (Cadeka/Exar) CDK2308BILP64 is a dual-channel, 10-bit analog-to-digital converter (ADC) sampling at up to 40 MSPS per channel, housed in a 64-pin QFN (9x9 mm) package. The "B" speed-grade variant of the CDK2308 family delivers 40 MSPS operation while sharing the same pinout as the 20/65/80 MSPS A/C/D grades, making it a flexible choice when designers want a single PCB layout to support multiple performance tiers. Each channel integrates a high-linearity track-and-hold amplifier (THA) optimized for IF frequencies up to 100 MHz. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and converts them into discrete digital codes for processing by FPGAs, DSPs, or microcontrollers. Within the converter hierarchy, the CDK2308BILP64 sits in the medium-speed, dual-pipeline ADC category, bridging low-power SAR ADCs (used for DC/multi-channel data acquisition) and high-speed pipelined ADCs (>100 MSPS, single-channel). This places it squarely inside the Power Management / Mixed-Signal IC family tree: ADC -> data converter -> mixed-signal IC -> integrated circuit. Key features include 10-bit resolution, 40 MSPS sample rate per channel, dual simultaneous sampling channels, low power consumption, and an integrated high-linearity THA. The device supports several independent power-down modes (per-channel, standby, full power-down) optimized for portable and battery-operated systems. The 64-QFN package offers an exposed thermal pad for low thermal resistance, critical at sustained high sample rates. The architecture is a fully differential pipelined ADC with on-chip sample-and-hold, voltage reference, and clock-receiver circuits. The pipeline design achieves low latency (a few clock cycles) and low spurious content while maintaining small die area. According to the Cadeka datasheet, SINAD and SFDR performance are characterized across input frequencies up to Nyquist. Typical applications include portable ultrasound imaging, IF sampling in communications receivers, low-cost digital oscilloscopes, handheld test instruments, and dual-channel data acquisition cards. The wide input bandwidth also makes it suitable for software-defined radio front-ends. When designing with this device, ensure the analog input drive is AC-coupled (or DC-coupled with proper common-mode biasing) and that the clock source meets the datasheet jitter requirement (<1 ps RMS) to preserve SNR at higher input frequencies. Use a solid ground plane under the exposed pad to minimize thermal rise and digital noise coupling. This page synthesizes distributor pricing, drop-in alternatives, and design guidance not found in the standalone manufacturer datasheet. Engineers evaluating the CDK2308BILP64 for production should also consider the A, C, and D speed-grade variants within the same footprint for BOM consolidation across product families.
CDK2308CILP64 - Dual 10-bit 65MSPS ADC | 64-QFN EP | MaxLinear
The MaxLinear (formerly Exar/Cadeka) CDK2308CILP64 is a dual-channel, 10-bit pipelined analog-to-digital converter sampling at up to 65 MSPS per channel, packaged in a 64-pin QFN with exposed pad for low thermal impedance. Each channel integrates a high-bandwidth track-and-hold and a multi-stage pipeline core, supporting full-power input bandwidths suitable for intermediate-frequency sampling in communications and imaging systems. The CDK2308CILP64 operates from a single 3.3 V analog supply and a separate 1.8 V to 3.3 V digital output supply, allowing direct interface to ASICs, FPGAs, or DSPs at multiple logic levels. An analog-to-digital converter (ADC) is a mixed-signal data-acquisition component that converts a continuous-time analog input voltage into a discrete digital code at a defined sample rate. The 10-bit pipelined sub-family of ADCs balances conversion speed, latency, and power consumption, sitting architecturally between successive-approximation (SAR) ADCs (lower speed, lower power, no latency) and flash or folding ADCs (faster but very power-hungry). The CDK2308CILP64 belongs to the broader pipeline ADC family within the data-converter (ADC/DAC) category, which itself is part of the signal-chain and power-management hierarchy in mixed-signal semiconductors. Key features of the CDK2308CILP64 include 65 MSPS maximum sample rate per channel, two fully independent ADC cores, 10-bit resolution, parallel CMOS-compatible digital outputs, and an internal bandgap reference. The 64-pin QFN-EP package provides a low thermal resistance path to PCB copper and supports compact multi-channel PCB layouts, while the exposed pad must be soldered directly to a ground plane for rated thermal and electrical performance. Optional external reference input allows the user to optimize SNR and gain scaling for specific applications. Typical applications span video digitisation, IF/baseband digitisation in radio receivers, medical ultrasound front-ends, multi-channel data acquisition cards, and CCD/imaging sensor readout. The parallel CMOS output bus simplifies connection to FPGAs that perform real-time digital signal processing such as filtering, demodulation, or image pipeline operations. Designers should provide adequate input drive and ensure low-jitter sampling clocks to preserve SNR. Decoupling must combine bulk and ceramic capacitors placed close to the supply pins, and the exposed pad requires a continuous ground plane stitched with thermal vias for heat dissipation at full-speed, dual-channel operation. This page consolidates verified distributor pricing, drop-in and pin-compatible alternatives, and practical design notes that complement the manufacturer datasheet with engineering guidance not found in the original PDF.
CDK2308DILP64 - Dual 10-bit 80MSPS ADC, 64-QFN | MaxLinear
The MaxLinear CDK2308DILP64 is a dual-channel, 10-bit analog-to-digital converter (ADC) supporting sample rates of 20, 40, 65, and 80 MSPS, packaged in a 64-pin QFN (9x9 mm) outline. It integrates two independent ADC channels, each preceded by a highly linear Track-and-Hold Amplifier (THA) optimized for input frequencies up to several hundred MHz, and it consumes 78 mW per channel at 80 MSPS. The device accepts single-ended analog inputs and is designed for low-power, high-dynamic-performance applications such as imaging, communications baseband, and portable instrumentation. An ADC (Analog-to-Digital Converter) is a data conversion integrated circuit that transforms continuous-time analog signals into discrete digital codes at a specified sampling rate, forming the critical bridge between the analog front end and the digital signal processing domain in mixed-signal systems. ADCs are classified by resolution (8/10/12/14/16-bit), sampling rate (kSPS to GSPS), and architecture (SAR, pipeline, sigma-delta, flash); the CDK2308 is a low-power pipeline ADC optimized for IF/RF baseband and video bandwidths. Key features of the CDK2308DILP64 include dual 10-bit resolution, programmable sample rates (20/40/65/80 MSPS), 78 mW power dissipation per channel at full speed, several independent power-down modes (channel standby, chip standby, full power-down) for battery-friendly operation, and a fast startup time that lets the converter leave idle mode with minimal latency. The 64-QFN package offers excellent thermal performance and a small 9x9 mm PCB footprint suitable for dense multi-channel receiver designs. The CDK2308DILP64 uses a pipelined architecture with internal reference and proprietary input THA design. Each channel can be independently powered down while the partner channel remains active, allowing asymmetric duty cycling in time-multiplexed systems. The wide input bandwidth and low aperture jitter make the part well suited to undersampling IF signals in software-defined radio and to digitizing CCD/CIS outputs in industrial camera front-ends. Typical applications include communications IF/baseband digitizers, set-top box and cable modem tuners, portable/low-power imaging systems, CCD/CIS sensor front-ends, and general-purpose high-speed data acquisition. In imaging, the dual-channel architecture can directly digitize RGB or stereo video streams without an external mux. When designing with the CDK2308DILP64, place the analog input traces as matched 50-ohm (or 75-ohm) controlled-impedance lines, keep the analog and digital ground returns separated until they join at the exposed pad, and provide a low-noise, low-dropout LDO for AVDD to preserve SNR. A 0.1 uF X7R bypass cap placed within 3 mm of each supply pin is essential. This page synthesizes distributor pricing, drop-in alternatives sourced from the same CDK2308 family and web-data cross-references, and practical PCB design notes not found in the standalone datasheet.
CDK2308DITQ64X - Dual 10-bit ADC, 80MSPS, TQFP-64 | MaxLinear
The MaxLinear CDK2308DITQ64X is a dual 10-bit analog-to-digital converter supporting 20/40/65/80 MSPS sampling rates, housed in a 64-pin TQFP package. The device integrates two ADC channels with internal reference circuitry, a CMOS control interface, and CMOS output data, all based on a proprietary architecture. The converters operate from a single 3.3 V supply and consume low power, making them well-suited for portable and high-density multi-channel data acquisition systems. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltage or current signals into discrete digital codes at a defined sampling rate. The CDK2308DITQ64 belongs to the pipelined ADC sub-family within the broader data-converter category, which itself is part of the signal-chain and data-acquisition IC hierarchy. Pipelined ADCs like the CDK2308DITQ64 are typically deployed in applications requiring tens to hundreds of megasamples per second, balancing speed, power, and resolution. Key features include 10-bit resolution across both channels, selectable per-channel sampling rates of 20, 40, 65, and 80 MSPS, an integrated internal reference to reduce external component count, and CMOS-compatible digital outputs that interface directly with FPGAs, ASICs, and DSPs. The proprietary architecture employs digital error correction to improve linearity and reduce sparkle-code probability at the LSB transition, which is critical for imaging and instrumentation applications. Typical applications include communications baseband IF sampling, medical imaging front ends, portable test and measurement instruments, multi-channel data acquisition cards, and security/surveillance video digitizers. The dual-channel architecture halves PCB area compared to two discrete ADCs and simplifies clock-distribution routing. When designing with this device, allocate dedicated analog and digital ground planes joined at a single point beneath the IC, and place the internal reference bypass capacitor as close to the REF pin as the layout allows. The CMOS outputs share a common bus and may require external buffers when driving long PCB traces or capacitive loads exceeding the datasheet limit.
CDK8307AILP64 - 12/13-bit Octal Ultra-Low Power LVDS ADC | MaxLinear
The MaxLinear CDK8307AILP64 is a 12/13-bit resolution, 20/40/50/65/80 MSPS, eight-channel ultra-low-power analog-to-digital converter (ADC) with serial LVDS outputs, housed in a 64-pin QFN package (ILP64 suffix). Each of the eight channels can be independently powered down, and a full-chip idle mode can be asserted through a single external pin whose function is configured via the serial control interface. The ADC integrates an internal reference and is based on a proprietary low-power architecture aimed at reducing system-level power dissipation in high-channel-count signal chains. A pipelined ADC is a high-speed converter architecture that uses multiple low-resolution stages to digitize an analog signal, trading slightly higher latency than successive-approximation converters for dramatically higher sample rates and multi-channel integration. The CDK8307 family positions itself within the analog-to-digital converter hierarchy as a multi-channel data-acquisition building block used in the broader mixed-signal and data-converter IC family. Each LVDS (Low-Voltage Differential Signaling) output serializes the conversion result onto a small number of differential pairs, simplifying board routing and enabling direct FPGA connectivity. Key specifications include 12/13-bit selectable resolution, sample rates of 20/40/50/65/80 MSPS, eight simultaneously-sampling channels, internal reference circuitry, and per-channel plus global power-down modes for energy-aware system design. The device is designed to interface directly with FPGAs from leading vendors, with LVDS serial output streams aligned for easy capture in the FPGA's high-speed transceiver or LVDS buffer logic. The proprietary architecture achieves low power per channel while maintaining AC performance across the supported sample-rate range. Typical applications include medical imaging systems, multi-channel communications infrastructure, portable and battery-powered test equipment, industrial data acquisition modules, and any multi-sensor array requiring synchronized eight-channel sampling. Per-channel shutdown allows unused channels to be turned off, reducing the average power consumption of a partially populated system significantly compared with always-on designs. Designers should plan decoupling close to each supply pin and follow the LVDS output routing guidelines in the manufacturer datasheet to maintain signal integrity across the eight serial lanes. The serial programming interface allows per-channel resolution selection, sample-rate configuration, and shutdown control, enabling software-defined power management. No mid-band analog trim is required thanks to the integrated internal reference.
CDK8307BILP64 - Octal 12/13-bit 40MSPS LVDS ADC | MaxLinear
The MaxLinear (formerly Exar/Cadeka) CDK8307BILP64 is an octal 12/13-bit analog-to-digital converter that samples at 20, 40, 50, or 65 MSPS per channel while consuming only 280 mW total. It outputs data over a serial LVDS interface and is housed in a 64-pin QFN package (LP suffix). The eight integrated ADCs share an internal reference and a serial control interface, and a built-in PLL multiplies the incoming sampling clock by 12 or 14 according to the LVDS output mode, which removes the need for an external high-frequency clock source. An analog-to-digital converter is an integrated circuit that samples continuous analog voltage levels and converts them into discrete digital codes for downstream processing. The CDK8307 belongs to the pipelined multi-channel ADC family (a successor to successive-approximation and flash architectures) and is widely used in medical imaging, sonar, industrial inspection, and multi-channel data acquisition systems where several signals must be captured simultaneously from a common clock edge. Key features include a programmable 12- or 13-bit resolution mode, an integrated low-jitter PLL, an internal bandgap reference, per-channel power-down control, and LVDS-compatible serial outputs that minimize EMI in dense multi-channel layouts. The PLL generates the internal ADC clock from a low-frequency reference, simplifying board design when the host FPGA or ASIC cannot supply a clean high-frequency sampling clock. The serial LVDS interface transmits the eight conversion streams over a reduced pin count compared with parallel CMOS ADCs. The CDK8307 architecture is built on a proprietary multi-stage pipeline that re-uses a sample-and-hold section across cycles, achieving the ultra-low power profile that distinguishes this part. Per-channel power-down allows unused channels to be gated when system requirements change, and the integrated reference reduces external BOM. The PLL-supported clock multiplication delivers deterministic sample timing across all eight channels simultaneously. Typical applications include portable and cart-based ultrasound beamforming, multi-channel sonar arrays, industrial flaw detection, and multi-axis vibration monitoring systems. The 280 mW total dissipation makes the CDK8307 particularly attractive for hand-held or battery-powered imaging systems where thermal budget is constrained. The combination of octal integration, LVDS outputs, and ultra-low power is the reason this part appears in mainstream ultrasound front-end designs. When designing with this device, allocate a continuous ground plane beneath the QFN thermal pad and stitch vias to inner ground layers to keep digital return currents away from the analog inputs. Drive each analog input through an AC-coupling network followed by a wide-bandwidth differential driver; the LVDS outputs require a 100-ohm termination at the receiver side. Always enter the recommended power-up sequence documented in the manufacturer datasheet before applying the analog inputs. This page synthesizes real-time distributor pricing, drop-in alternatives verified against the 64-pin QFN footprint, and practical multi-channel ADC design notes not aggregated elsewhere in a single view.
CDK8307CILP64 - 12/13-bit 65MSPS Octal ADC, LVDS Output | MaxLinear
The MaxLinear (formerly Exar/Cadeka) CDK8307CILP64 is a 12/13-bit, 65 MSPS, eight-channel ultra-low-power analog-to-digital converter with serial LVDS output, housed in a 64-pin LQFP (LP64) package. It is a high-performance, low-power octal ADC employing internal reference circuitry, a serial control interface, and a proprietary pipeline architecture optimized for simultaneous sampling across all eight channels. The device supports multiple speed grades (20/40/50/65 MSPS) within the same pinout, allowing one PCB to serve multiple system requirements. An octal ADC is a data converter that integrates eight independent analog-to-digital conversion channels into a single silicon die. Each channel samples its analog input at the same clock edge, converting up to 65 million samples per second, and outputs the digital codes through a low-voltage differential signaling (LVDS) bus. The LVDS interface reduces EMI and supports high-speed board-to-FPGA or board-to-ASIC transmission over twisted-pair or controlled-impedance traces. Octal ADCs sit in the broader signal chain hierarchy: analog front end -> ADC -> digital processor (FPGA/ASIC/DSP) -> application. This integration reduces board area, BOM count, and channel-to-channel skew in multi-channel systems. Key features include 12/13-bit selectable resolution, 65 MSPS maximum sample rate, 8 simultaneous sampling channels, integrated bandgap reference, serial LVDS digital outputs, low power consumption (a key feature for portable and densely-populated systems), and an SPI-compatible serial control interface for mode configuration. The 64-pin LQFP package supports standard surface-mount assembly, with the exposed-pad variant providing enhanced thermal dissipation. Pin compatibility with the broader CDK8307 family (20/40/50/65/80 MSPS grades) allows design scalability within a single PCB layout. The CDK8307 architecture uses a proprietary pipeline structure that achieves excellent dynamic performance while minimizing power consumption per channel. Internal reference circuitry eliminates the need for external reference components, simplifying the BOM and reducing the analog front-end footprint. The serial LVDS interface operates at one or two lanes per channel, with low jitter that preserves signal integrity in cascaded systems. The SPI control port allows the host processor to configure resolution, test patterns, output format, and channel power-down modes without external hardware. Typical applications include medical ultrasound imaging (where the octal simultaneous sampling directly maps to the 8-to-128 element transducer array), portable instrumentation, multi-channel data acquisition systems, industrial non-destructive testing (NDT), and security/surveillance imaging. The ultra-low-power profile makes it especially well suited to handheld and battery-powered imaging systems where thermal density is constrained. A key design consideration is the LVDS data rate: at 65 MSPS with 13-bit two-lane output, the per-channel serial data rate approaches 1 Gbps, requiring controlled-impedance routing (typically 100 ohm differential), length matching within 5 ps, and AC coupling at the receiver. Decoupling the AVDD pins with both bulk and high-frequency ceramic capacitors placed as close to the pins as possible is critical to achieving the datasheet SNR/SFDR performance. This page synthesizes distributor pricing, drop-in alternatives within the CDK8307 family, and practical design notes not consolidated in any single manufacturer document.
CDK8307DILP64 - 12/13-bit 65MSPS Octal ADC, LVDS, 64-QFN | MaxLinear
The MaxLinear CDK8307DILP64 is a 12/13-bit, 65 MSPS, eight-channel ultra-low-power analog-to-digital converter (ADC) with serial LVDS outputs, housed in a 64-pin QFN (9x9 mm) package. It supports sample rates of 20/40/50/65 MSPS, features an internal reference, a serial control interface, and proprietary multi-channel architecture. The device operates from a 1.8 V analog supply and 1.7-3.6 V digital supply, making it well suited to power-sensitive multi-channel systems. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts real-world analog signals (voltage, current, sensor outputs) into discrete digital codes for processing by microcontrollers, FPGAs, or DSPs. Multi-channel ADCs like the CDK8307 integrate several ADC cores in one package, sharing clocking and reference circuits, and are widely used in medical imaging, communications infrastructure, and industrial test equipment. In the broader component taxonomy, the CDK8307 sits as: ADC -> data converter -> mixed-signal IC -> semiconductor device. Key specifications include 12/13-bit resolution, 65 MSPS maximum sample rate, eight simultaneous sampling channels, low power consumption (around 45 mW per channel at 65 MSPS), and LVDS (Low-Voltage Differential Signaling) serial outputs that minimize digital EMI on the PCB. The proprietary internal architecture provides high spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) suitable for demanding IF-sampling applications. The CDK8307 uses a proprietary pipelined core with internal reference circuitry and a serial control interface (SPI-compatible) for mode programming. Its LVDS outputs allow the ADC to be placed close to the analog source while routing digital data long distances over differential pairs, reducing ground bounce and digital coupling into analog sections. Typical applications include medical ultrasound imaging, multi-channel communications receivers, portable and battery-powered instrumentation, industrial data acquisition systems, and multi-antenna software-defined radio (SDR) platforms. The combination of eight channels, low power, and LVDS outputs makes it a strong fit for systems requiring many synchronized sample streams at low total power. When designing with this device, route LVDS pairs as 100-ohm differential transmission lines with length matching within 5 ps, and keep the analog and digital supply domains well decoupled near the package. Provide a low-jitter clock to the CLK input - jitter directly degrades SNR at high input frequencies, so budget no more than 1 ps RMS at the ADC clock pin. This page synthesizes distributor pricing, drop-in alternative cross-references, application notes, and design considerations not aggregated in a single location on the manufacturer's datasheet, including head-to-head comparison tables and PCB-level guidance for high-channel-count layouts.