ADC/DAC
Products (2398)
TLC5540CPWRG4 - 8-Bit 40 MSPS Flash ADC, 24-TSSOP | Texas Instruments
The Texas Instruments TLC5540CPWRG4 is an 8-bit, 40-MSPS (megasamples per second) flash analog-to-digital converter (ADC) with a single input channel and internal sample-and-hold, housed in a 24-pin TSSOP (PW) package. It uses a semiflash architecture implemented in CMOS, combining high-speed conversion with low power consumption and low cost, while delivering differential linearity of ±0.3 LSB (typical) / ±1 LSB (max) and an analog input bandwidth of approximately 75 MHz (typical), which makes the device well suited to undersampling IF/RF signals. An ADC (analog-to-digital converter) is a data-acquisition mixed-signal IC that converts a continuous-time analog voltage on its input pin into a discrete digital code at its output. Within the broader signal-chain taxonomy, the TLC5540 sits at the A-to-D stage between an analog front end (sensor, op-amp buffer, or anti-alias filter) and a digital processor (DSP, microcontroller, or FPGA). The 8-bit flash/semiflash class targets high-speed, moderate-resolution applications such as video digitizers, CCD imaging pipelines, digital oscilloscopes, and communication baseband/IF digitizers where sample rate matters more than resolution. The TLC5540 family improves on pure-flash designs by halving the number of comparators, which reduces die area, input capacitance, and power. Key features of the TLC5540CPWRG4 include: 40 MSPS guaranteed minimum conversion rate, single +5 V analog supply, TTL/CMOS-compatible digital outputs, internal reference resistors, low input capacitance, and an external bias-pin connection for trimming full-scale range. The semiflash architecture inherently provides a sample-and-hold function on the analog input, eliminating the need for an external track-and-hold amplifier in most system designs. Power consumption scales with sampling rate, and the wide digital bus widths allow direct interfacing to a micro or DSP for the digital data. Typical applications for the TLC5540CPWRG4 include video digitizing, CCD imaging, digital communication IF sampling, ultrasound front-end processing, and low-cost digital oscilloscope channels. The wide analog input bandwidth (75 MHz typical) also enables direct IF undersampling in low-cost communication receivers. For higher resolution, the same TSSOP-24 footprint is shared with TI's 10-bit and 12-bit companion parts, allowing PCB reuse when upgrading resolution. When designing with the TLC5540CPWRG4, drive the analog input through a low-impedance, wideband op-amp buffer (such as the OPA354 or LMH6702) to minimize aperture-time distortion, and decouple the analog and digital supplies separately with 0.1 µF ceramic capacitors placed close to the supply pins. Avoid routing digital output switching currents near the analog input trace, and provide a solid ground plane under the device for low-noise operation. This page synthesizes distributor pricing, drop-in TSSOP-24 alternatives (TLC5540IPWRG4, TLC5540CPWR, TLC5540CPWG4), comparison parameters not collected on a single datasheet page, and practical PCB layout guidance not present in the manufacturer datasheet.
TLV0834 - 8-Bit 41 kSPS 4-Ch SAR ADC | Texas Instruments
The Texas Instruments TLV0834 is a low-power, 8-bit successive-approximation register (SAR) analog-to-digital converter with a software-configurable 4-channel input multiplexer supporting single-ended, differential, and pseudodifferential input assignments. It operates from a 2.7V to 3.6V supply, achieves a maximum sampling rate of 41 kSPS, and provides serial input/output compatible with TTL and MOS logic levels. Packages include 16-pin TSSOP (PW) and 16-pin SOIC (D). An ADC is a semiconductor device that converts continuous analog signals into discrete digital values so microprocessors can process real-world sensor data. The TLV0834 belongs to the SAR ADC family, which balances speed, resolution, and power for medium-speed data acquisition, within the broader hierarchy of data converter ICs and mixed-signal semiconductors. Key features include 8-bit resolution with no missing codes, 41 kSPS maximum throughput, a 2/3/4-channel multiplexer with software address logic, and differential input capability that enables common-mode rejection or offset of the analog zero point. The device operates ratiometrically or with a VCC reference, simplifying reference design in low-voltage systems. Architecturally, the TLV0834 uses a sample-data comparator performing successive approximation on the selected differential input pair. The serial interface minimizes pin count and supports easy microprocessor interface or stand-alone operation. The analog input range spans from ground (0 V) to VCC when using the VCC reference, covering the full supply span without external scaling in many designs. Typical applications include portable and battery-powered instrumentation, multi-channel industrial data acquisition, and remote sensor monitoring. Low supply voltage and serial output make it compatible with modern microcontrollers and DSPs such as the TI MSP430 family. Design consideration: never let analog inputs exceed VCC, and decouple the supply with a 0.1uF ceramic capacitor close to the pin for stable conversions. Prices referenced are as of 2026-08-29.
TLV0834CPWRG4 - 8-Bit 41kSPS 4-Ch SAR ADC, 16-TSSOP | Texas Instruments
The Texas Instruments TLV0834CPWRG4 is an 8-bit, 41 kSPS, successive-approximation analog-to-digital converter (SAR ADC) with 2/3/4 configurable input channels and a serial interface, housed in a 16-pin TSSOP package. It operates from a single 2.7 V to 3.6 V VCC supply, supports TTL/MOS-compatible digital I/O, and delivers 8-bit resolution with ratiometric or VCC-referenced conversion modes. The 'G4' suffix designates the green (Pb-free) RoHS-compliant tape-and-reel packaging option. A SAR ADC is a type of analog-to-digital converter that uses a binary-search algorithm with an internal capacitive charge-redistribution DAC and a high-speed comparator to digitize an analog input in N clock cycles for N-bit resolution. Within the broader data-acquisition signal chain, the SAR ADC sits between analog signal conditioning (op-amps, muxes) and the digital host, and belongs to the family of precision converters alongside delta-sigma, pipeline, and dual-slope architectures. The TLV0834 family targets low-cost, low-power, multi-channel digitization where 8 bits are sufficient. Key features include 41 kSPS throughput, 2.7 V to 3.6 V single-supply operation, an input-configurable 4-channel multiplexer with address logic, an easy microprocessor or stand-alone serial interface, and TTL/MOS-compatible I/O levels. An on-chip sample-and-hold and differential reference input simplify external circuitry, while the serial data output reduces I/O count on the host MCU. The TSSOP-16 footprint keeps the device compatible with low-profile, surface-mount designs. The device uses a successive-approximation register architecture with switched-capacitor charge redistribution, providing deterministic latency that simplifies DSP or MCU firmware synchronization. Its low current consumption (~0.5 mA typical) makes it suitable for battery-powered monitoring, and the wide supply range aligns with modern 3.3 V microcontroller rails. Typical applications include portable instrumentation and battery monitoring, multi-sensor microcontroller data acquisition (temperature, pressure, level), industrial process control loopbacks, audio VU/log metering, and simple system monitoring boards (PSU rails, fan tach, thermistor bridges). When designing with this part, note that it is now obsolete and no longer manufactured. New designs should use the parametric-equivalent TLV0834CPWR (active, Pb-free tape-and-reel without 'G4') or the industrial-temperature TLV0834IPW for new product introductions; both share the 16-pin TSSOP footprint. Plan for last-time-buy inventory or substitute selection accordingly. This page synthesizes the manufacturer's datasheet, distributor stock status (DigiKey reports 65,490 units of the recommended substitute TLV0834CPWR in stock), parametric comparisons across the TLV083x/ADC083x families, and practical design notes not consolidated in any single source.
TLV0838ING4 - 8-Bit 8-Ch SAR ADC, 3.6V, Serial I/O | Texas Instruments
The Texas instruments TLV0838ING4 is an 8-bit successive-approximation analog-to-digital converter with an input-configurable multichannel multiplexer and a serial I/O interface, supplied in a 20-pin PDIP package and operating from a 2.7 V to 3.6 V single supply. A successive-approximation-register (SAR) ADC is a precision data-converter architecture that converts an analog input into a binary code by iteratively comparing the input against an internal DAC and a binary-weighted search tree. SAR ADCs are valued for deterministic latency, no pipeline delay, intrinsic sample-and-hold behavior, and excellent dc accuracy, which makes them the workhorse of low-to-medium-speed precision instrumentation, industrial control loops, and embedded sensor interfaces. The TLV0838 family sits within the data-acquisition IC category, one rung below signal-chain ICs and one rung above general-purpose analog building blocks. Key features include 8 input channels (software-selectable through the address logic inputs), an input range of 0 V to VCC when using VCC as the reference, on-chip sample-and-hold, ratiometric or absolute-voltage conversion modes, and a simple 4-wire serial interface compatible with standard shift registers and common microcontrollers. Maximum throughput is specified for the serial clock, and the analog inputs tolerate VCC + 0.3 V without damage. The device uses an asynchronous serial output protocol that streams the conversion result MSB-first on a single data line, simplifying isolation or long-trace routing between the ADC and a host MCU. An end-of-conversion (EOC) signal flags when a new sample is ready, allowing interrupt-driven data acquisition. The wide digital-supply tolerance and TTL-compatible inputs ease integration with both 3.3 V and 5 V logic families. Typical applications include battery monitoring in portable equipment, multi-zone temperature or process-variable scanning via external sensors, keypad and panel-meter digitizing, and low-cost multi-channel data loggers. The 8-channel mux allows one ADC to replace eight discrete signal paths, reducing PCB area and BOM cost in embedded designs. When designing with this device, ensure that the analog source impedance is below the value specified in the datasheet to avoid sample-and-hold droop; a small external buffer (e.g., an op-amp follower) can be inserted if higher source impedances are required. Decouple VCC with both a 0.1 uF ceramic and a bulk capacitor placed within 5 mm of the supply pin. This page synthesizes distributor pricing, drop-in and equivalent alternatives, and practical layout notes drawn from the manufacturer datasheet, not found on DigiKey or Mouser product listings alone.
TLV1504IDR - 10-Bit 200kSPS 4-Ch SAR ADC, SOIC-16 | TI
The Texas Instruments TLV1504IDR is a 10-bit, 200 kSPS, 4-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) with a serial interface, housed in a 16-pin SOIC (D) package. It operates from a single 2.7 V to 5.5 V analog and digital supply, draws only 1.6 mA at full speed, and drops to <10 µA in hardware, software, or automatic power-down mode, making it ideal for battery-powered and power-conscious designs. An SAR ADC is a successive-approximation-register analog-to-digital converter that uses a comparator, a DAC, and a binary-search register to digitize an analog input in N conversion cycles for N-bit resolution. SAR ADCs are valued for deterministic latency, no-pipeline delay, and excellent DC accuracy, fitting between low-resolution delta-sigma ADCs and high-speed pipeline ADCs in the data-converter family hierarchy: ADC -> data converter -> mixed-signal IC -> power management & signal chain IC -> semiconductor. Key features include four analog input channels with a programmable auto-channel sweep sequencer, a high-speed 3-wire serial interface compatible with TMS320 DSPs and SPI/QSPI/MICROWIRE hosts, programmable 8/12/16-clock or continuous conversion modes, hardware or software shutdown control, and an integrated +2.5 V reference option (TLV1504 variant) or external-reference option. Maximum conversion time is 3.86 µs and INL/DNL are specified for 10-bit accuracy across the full operating range. Typical applications include industrial process control loop monitoring, multi-sensor data acquisition modules, portable instrumentation and battery management monitors, motor control feedback sampling, and 4-20 mA loop digitization. The wide 2.7 V to 5.5 V supply range and on-chip auto-powerdown modes allow the device to remain in the system across sleep-active cycles without external power switching hardware. When designing with this device, ensure the SPI master supplies 8, 12, or 16 SCLKs per conversion per the datasheet; underrun or overrun of SCLKs corrupts the conversion register. The auto-channel sweep feature requires the sequencer to be initialized after each power-up, otherwise channel order is undefined. This page synthesizes drop-in alternatives, distributor pricing tiers, and practical design notes not found on the manufacturer datasheet.
TLV1504IDRG4 - 10-Bit 200kSPS 4-Ch SAR ADC | Texas Instruments
The Texas Instruments TLV1504IDRG4 is a 10-bit, 200-kSPS, 4-channel successive-approximation-register (SAR) analog-to-digital converter housed in a 16-pin SOIC package. It operates from a single 2.7 V to 5.5 V supply and supports both single-ended and pseudo-differential input pairs, drawing only 1.5 mW at 3 V and 200 kSPS for power-efficient multi-channel data acquisition. What is a SAR ADC? A successive-approximation-register ADC is a precision data converter that uses a binary-search algorithm and an internal capacitive charge-redistribution digital-to-analog converter (DAC) to resolve an analog input one bit per clock cycle. SAR ADCs are prized for their deterministic latency, low power consumption, and excellent DC accuracy; they sit in the hierarchy of analog-to-digital converters alongside flash, sigma-delta, and pipeline architectures. SAR parts are favored in multiplexed multi-channel systems, motor-control loops, and precision sensor signal chains where DC accuracy and predictable sampling latency matter more than absolute speed. Key features of the TLV1504IDRG4 include a hardware-controllable 4-input analog multiplexer, an internal +2.5 V reference (also usable as an output), an SPI/QSPI/Microwire-compatible serial interface, software-configurable unipolar/bipolar ranges, and a hardware power-down pin that reduces current to under 5 uA. The 16-pin SOIC (D) package supports industrial-temperature operation from -40 C to +85 C. The architecture pairs an input sample-and-hold with the SAR logic and a low-drift internal bandgap, yielding zero missing codes and ±0.5 LSB typical INL/DNL. The wide 2.7 V to 5.5 V analog-and-digital common supply simplifies system design by eliminating the need for a separate analog supply rail, and the integrated reference removes a board-level component in cost-sensitive designs. Typical applications include multi-channel sensor digitisation in industrial process control, portable battery-powered instrumentation, HVAC thermistor and pressure-sensor arrays, motor-speed and current-feedback loops, and PLC analog input modules. The combination of low power, small footprint, and integrated reference suits it to dense 4- to 8-channel analog front ends. When designing with this ADC, decouple AVDD and DVDD separately with 0.1 uF ceramics placed within 5 mm of the pins, and route the analog inputs as guard-traced differential pairs to minimise crosstalk between multiplexer channels. Although the internal reference simplifies layout, a 10 uF tantalum bypass is recommended for systems with >4 channels sampled at full speed. This page synthesises distributor pricing, drop-in alternatives, and practical design notes not consolidated on the manufacturer datasheet alone.
TLV1508IDWRG4 - 10-Bit 200kSPS 8-Ch Serial ADC | Texas Instruments
The Texas Instruments TLV1508IDWRG4 is a 10-bit, 200 kSPS, low-power, CMOS successive-approximation analog-to-digital converter (SAR ADC) housed in a 20-pin SOIC (DW) package. It operates from a single 2.7 V to 5.5 V supply, offers 4 or 8 analog input channels with a 3.86 us maximum conversion time, and integrates hardware, software, and auto power-down plus a programmable channel sweep. The serial interface uses a 4-wire SPI-compatible bus (CS, SCLK, SDI, SDO). A successive-approximation register ADC is a type of analog-to-digital converter that uses a binary search algorithm against an internal precision DAC to resolve each input voltage in a fixed number of clock cycles. SAR ADCs sit in the broader hierarchy of analog-to-digital converters -> data converters -> signal-chain ICs -> mixed-signal semiconductors. Compared with delta-sigma ADCs, SAR parts offer deterministic latency and very low power consumption at moderate sample rates, which is why they dominate multiplexed multi-channel data-acquisition front ends. Key specifications include 0.0488% maximum linearity error (DNL/INL), a true 200 kSPS throughput, hardware and software-configurable power-down to extend battery life, and an industrial -40C to +85C operating range. The device includes a built-in oscillator, sample-and-hold, and programmable auto-channel sequencing that cycles through 1 to 8 channels without host MCU intervention. Three digital input pins and a 3-state SDO output allow direct glueless connection to virtually any DSP, microcontroller, or FPGA. Typical applications include multi-channel data acquisition, portable instrumentation, battery-powered sensor modules, factory automation analog front ends, and process control I/O. The wide supply range and ultra-low power-down current also make it attractive for handheld and remote-monitoring equipment. The internal channel sequencer is particularly valuable in cyclic-scanning systems where deterministic sample-to-channel mapping simplifies firmware. Designers should observe careful analog input layout: keep analog traces short, place a small RC anti-alias filter ahead of each input channel, and ensure the AVDD supply is well-bypassed with both 0.1 uF and 10 uF capacitors close to the pin. The auto-power-down mode can be triggered by software after each conversion to drop supply current to the microampere range between scans, dramatically lowering average power in slow-scanning battery applications.
TLV1562IDWRG4 - 10-Bit 2MSPS Quad ADC w/4-CH Mux | TI
The Texas Instruments TLV1562IDWRG4 is a 10-bit, 2 MSPS reconfigurable low-power analog-to-digital converter with a four-input analog multiplexer, dual sample-and-hold, parallel interface and power-down mode, housed in a 28-pin SOIC (DW) package. Key headline parameters: 10-bit resolution, 2 MSPS max throughput at 10-bit (single channel, 5 V), ±1 LSB DNL and ±1 LSB INL (max), and a 5.5 V absolute-maximum analog input. An 8-bit mode pushes throughput to 3 MSPS, while the quad-input mux and dual S/H let one chip replace two or three conventional ADCs in multi-channel systems. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog waveform and quantizes each sample into a binary code word. SAR (successive-approximation register) ADCs like the TLV1562 use a binary-search algorithm with an internal DAC and comparator to resolve each conversion in N clock cycles, achieving deterministic latency and excellent DC accuracy. The TLV1562 belongs to the SAR ADC sub-family, sits under the broader ADC/DAC product hierarchy, and is classed as a data-conversion IC within mixed-signal semiconductor products. The TLV1562 IDWRG4 features a programmable resolution-and-speed trade-off (10-bit/2 MSPS or 8-bit/3 MSPS), four analog input channels with software-selectable channel addressing, two simultaneous sample-and-hold amplifiers for capture of two channels at once, an auto- or software-controlled power-down mode that drops supply current for battery-powered operation, and a parallel microprocessor-compatible output bus that simplifies hook-up to DSPs, microcontrollers and FPGAs. Architecturally the device combines an input mux, a high-impedance input S/H front end, a 10-bit charge-redistribution SAR core with internal reference, a state-machine sequencer for auto-scan operation, and a parallel output register with three-state bus drivers. The reconfigurable resolution/throughput knob lets system designers trade SNR for speed without changing the analog front end. Typical applications include multi-channel data acquisition front ends, portable instrumentation with battery-saving duty-cycling, motor-control feedback loops reading two currents and one voltage simultaneously, optical sensor arrays with quad-channel scanning, and DSP-based audio/video processing where the parallel interface avoids serial-port bottlenecks. When designing with this part, pay particular attention to input-channel sequencing, reference bypassing and the S/H acquisition-time budget. Choosing software-mode power-down reduces IDD to a few hundred microamps between conversions - useful for handheld instruments where the ADC must wake, convert a burst and return to sleep. This page synthesizes distributor pricing, drop-in alternatives in the same 28-SOIC footprint and practical design notes not found on the manufacturer datasheet cover page.
TLV2544QDRG4 - 12-Bit 200kSPS 4-Ch SAR ADC | Texas Instruments
The Texas Instruments TLV2544QDRG4 is a 12-bit, 200-kSPS, 4-channel, low-power, serial-output successive-approximation-register (SAR) analog-to-digital converter with AutoPower-Down, supplied in a 16-pin SOIC (D) package. It operates from a single 3 V to 5.5 V analog supply, integrates a built-in reference, conversion clock, and an 8× FIFO, and targets cost- and power-sensitive multi-channel data-acquisition systems. The Q-suffix designates the automotive temperature grade (-40 °C to +125 °C), and the G4 suffix denotes tape-and-reel packaging with Pb-free finish. A SAR ADC is a type of analog-to-digital converter that uses a binary-search algorithm against a precision DAC to resolve each input sample in N clock cycles, where N is the resolution in bits. SAR ADCs offer deterministic latency, no pipeline delay, excellent dynamic performance at moderate sample rates, and very low standby power - features that make them ideal for multiplexed sensor systems, motor-control feedback loops, and instrumentation where every conversion must complete in a known time. The TLV2544QDRG4 inherits all of these SAR traits and adds hardware (CS) and software (S/W) AutoPower-Down control, dropping supply current after each conversion to extend battery life in portable and remote installations. The device digitizes up to four single-ended inputs through an internal analog multiplexer at up to 200 kSPS aggregate throughput, and provides a 4-wire SPI/QSPI/MICROWIRE-compatible serial interface. AutoPower-Down reduces quiescent current to a few microamps between conversions, and differential non-linearity / integral non-linearity errors are specified at ±1.2 LSB maximum up to 125 °C. A signal-to-noise-plus-distortion ratio above the SNR figure cited for the family supports 12-bit effective resolution at the full sampling rate. Architecturally, the TLV2544QDRG4 combines a charge-distribution DAC array, a high-bandwidth input sample-and-hold, an internal 2.5 V reference (or external reference option via REFin), a digital conversion-control state machine, and the AutoPower-Down timing block. The reference and oscillator are fully internal, eliminating external components and shrinking BOM cost in space-constrained systems. Typical applications include automotive sensor interfaces, multi-channel industrial process control, battery-powered portable instrumentation, motor-speed/temperature monitoring, and any multi-channel data logger that needs deterministic low-latency 12-bit conversion. Compared with the TLV2548Q (which is the 8-channel pin-compatible cousin of the same family), the TLV2544QDRG4 trades two analog input channels for a smaller BOM footprint when only four channels are required. During design, keep analog and digital grounds tied to a single star point near the AGND pin, decouple AVDD with a 10 µF tantalum plus 0.1 µF ceramic combination within 5 mm of the pin, and observe the device's 200 kSPS maximum throughput budget when sequencing multi-channel conversions.
TLV2545IDGKR - 12-Bit 200 kSPS Serial ADC | Texas Instruments
The Texas Instruments TLV2545IDGKR is a 12-bit, 200 kSPS successive-approximation analog-to-digital converter with a serial output, housed in an 8-pin VSSOP (DGK) package. Operating from a single 2.7 V to 5.5 V supply, the part features a 1-channel single-ended or pseudo-differential input, integrated conversion clock, autopower-down between conversions, and SPI/DSP-compatible serial interface that supports up to 10 MHz clock rates and TMS320 DSP connections. An ADC (analog-to-digital converter) is a data-conversion integrated circuit that samples a continuous analog voltage and produces a discrete digital code, and a successive-approximation-register (SAR) ADC does so by iteratively comparing the input against an internal DAC, achieving an excellent balance of speed, accuracy, and power consumption for precision low-frequency and audio-bandwidth signals. The TLV2545 belongs to the broader hierarchy of data-converter ICs, which sit within signal-chain and power-management semiconductor families. Key features of the TLV2545 include ±1 LSB maximum INL and DNL, 72 dB SINAD, and 85 dB SFDR at a 20 kHz input tone, along with a 3.5 µs typical conversion time and a flexible SCLK/FS-compatible serial interface. The autopower-down feature reduces current draw to a few microamps between conversions, which is critical for battery-powered and energy-harvesting applications where average load matters more than peak throughput. The architecture uses a charge-redistribution SAR core with an internal sample-and-hold and on-chip oscillator, eliminating the need for an external clock. The pseudo-differential input stage simplifies board layout by accepting ground-referenced signals without a negative rail, while the wide supply range permits direct interface to 3.3 V microcontrollers, 5 V DSPs, or low-voltage battery stacks. Typical applications include portable instrumentation, motor-control feedback loops, battery monitoring, sensor signal conditioning, point-of-load monitoring in industrial control, and audio-bandwidth digitization for consumer audio and telecommunications equipment. The 8-pin VSSOP footprint suits space-constrained designs. When designing with the TLV2545, place 100 nF decoupling close to the supply pin and follow layout practices that keep digital return currents away from the analog input. The SCLK clock rate must remain within the 10 MHz SPI specification, and CS falling-edge timing relative to SCLK should be reviewed against the TMS320 interface diagrams in the datasheet. This page synthesizes distributor pricing, drop-in same-package alternatives drawn from the same TI VSSOP-8 ADC family, and practical layout notes that go beyond what the manufacturer datasheet alone provides.
TLV2545IDGKRG4 - 12-Bit 200kSPS Serial ADC, MSOP-8 | Texas Instruments
The Texas Instruments TLV2545IDGKRG4 is a 12-bit, 200 kSPS, low-power, serial-interface analog-to-digital converter (ADC) using successive-approximation architecture in an 8-pin MSOP (DGK) PowerPAD package. It operates from a single 2.7 V to 5.5 V analog supply, supports a single pseudo-differential analog input, and includes a built-in conversion clock, an SPI/DSP-compatible serial interface up to 10 MHz, and an Auto-Power-Down mode that reduces current consumption to under 1 µA between conversions. An ADC (analog-to-digital converter) of this type is a precision data converter that quantifies an analog input voltage into a binary code. The TLV2545 belongs to the successive-approximation register (SAR) ADC family — a sub-class of general-purpose, low-latency converters — within the broader data-converter hierarchy of ADC/DAC ICs. SAR ADCs are favored when deterministic latency, simple serial interfacing, and low power dissipation are required, making them a common choice over delta-sigma ADCs for multiplexed or control-loop applications. Key features include ±1 LSB maximum INL and DNL, 72 dB SINAD, 85 dB SFDR at a 20 kHz input, 3.5 µs conversion time, Auto-Power-Down that activates at end-of-conversion, and TMS320-compatible serial output. The DGK MSOP-8 with PowerPAD provides a low thermal-resistance path, enabling reliable operation across the industrial -40 °C to +85 °C temperature range. The TLV2545 uses charge-redistribution SAR architecture with an internal sample-and-hold and a precision DAC. The integrated Auto-Power-Down dynamically reduces consumption to sub-microamp levels between conversions, allowing the part to serve battery-powered, event-driven, or polled systems without the overhead of an external analog switch. Typical applications include portable instrumentation and battery-powered sensors, industrial process control loops, multi-channel data-acquisition front-ends, digital signal processor (DSP) and microcontroller analog front ends, optical-networking monitoring, and touch-screen or panel-metering subsystems. When designing with this ADC, place the 1.5 nF CS capacitor and 10 µF bypass capacitor close to the supply pins, route the analog and digital grounds in a star or split-plane topology, and ensure the reference decoupling (REF decoupling capacitor) is short and noise-free. The internal oscillator and Auto-Power-Down mean no external clock is required for stand-alone operation. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical PCB-layout design notes that go beyond the manufacturer datasheet.
TLV5580IPWG4 - 8-Bit 80 MSPS Low-Power ADC | Texas Instruments
The Texas Instruments TLV5580IPWG4 is an 8-bit, 80 MSPS low-power analog-to-digital converter (ADC) with a pipelined architecture, housed in a 28-pin TSSOP (PW) package rated for the industrial -40C to +85C temperature range. The part delivers 700 MHz typical analog input bandwidth, internal top/bottom reference voltages, and an adjustable full-scale reference input for flexible system calibration. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous analog waveform and produces a discrete binary code proportional to the input amplitude. The TLV5580 belongs to the pipelined ADC family, which sits in the hierarchy: ADC -> data converter -> data acquisition IC -> mixed-signal semiconductor. Pipelined ADCs use multiple low-resolution stages to achieve high sample rates at modest power, making them a standard choice for IF-sampling communications, CCD imaging, and digital oscilloscope front ends. Key features of the TLV5580 include 80 MSPS maximum sampling rate, single 3.3 V supply operation, 3.3 V TTL/CMOS-compatible digital I/O that simplifies interface to modern FPGAs and ASICs, an internal bottom-plate reference that reduces external component count, and an adjustable reference input for gain trim. The 700 MHz analog input bandwidth supports undersampling architectures where the ADC digitizes IF frequencies well above Nyquist. The 28-TSSOP (PW) footprint is pin-compatible across the broader TLV/TLC ADC family from Texas Instruments. Architecturally the device uses a multi-stage pipeline with internal sample-and-hold and digital error correction. The combination of 80 MSPS and 8-bit resolution keeps per-conversion power low (single-digit mA from a 3.3 V rail), which is the original design target: applications where the ADC must sit on the same board as noisy digital logic without dominating the power budget. The TLV5580 has been replaced by the ADS831 in TI's portfolio but remains specified and available for legacy designs. Typical applications include CCD imaging digitizers, video capture front ends, IF-sampling communications receivers, portable battery-powered instrumentation, and digital oscilloscope input stages. In each case the part provides a compact, low-power, single-supply path from analog to digital. When designing with the TLV5580, decouple AVDD and DVDD separately close to the package and follow standard pipelined-ADC layout practice: keep analog input traces short, use a ground plane under the analog input, and provide a clean 3.3 V rail. The PW suffix indicates tube packaging; the device is also offered in tape and reel as TLV5580IPWR.
TLV5617A - Dual 10-Bit DAC, 2.7-5.5V | Texas Instruments
The TLV5617A is a dual 10-bit voltage output digital-to-analog converter (DAC) from Texas Instruments, designed for low-power and space-constrained applications. It operates from a single 2.7V to 5.5V supply and features a flexible 3-wire serial interface compatible with TMS320, SPI, QSPI, and Microwire serial ports. The device is available in an 8-pin SOIC package (TLV5617AID) and includes a power-down mode to conserve energy. A digital-to-analog converter (DAC) is an electronic circuit that converts digital binary data into an analog voltage or current. The TLV5617A is a voltage-output DAC, meaning it produces a voltage proportional to the digital input. It is part of the broader family of data converters, which are essential in mixed-signal systems where digital processing must interface with the analog world. DACs are used in applications such as audio playback, motor control, and sensor calibration. Key features of the TLV5617A include dual 10-bit resolution, programmable settling time (fast mode: 3 µs, slow mode: 10 µs), and a rail-to-rail output buffer with Class-AB stage. The device also offers a power-down mode that reduces quiescent current to 1 µA, making it ideal for battery-powered equipment. The serial interface accepts a 16-bit word consisting of 4 control bits and 10 data bits, allowing flexible configuration. The TLV5617A uses a resistor-string architecture with a x2 gain rail-to-rail output buffer, ensuring low glitch energy and monotonic performance. The output buffer can drive capacitive loads up to 100 pF without external compensation. The device is specified over the industrial temperature range of -40°C to +85°C and is RoHS compliant. Typical applications include programmable voltage sources, digital gain and offset adjustment, and industrial process control. The low power consumption and small package make it suitable for portable instrumentation and battery-powered devices. The serial interface simplifies connection to microcontrollers and DSPs, reducing board space and pin count. When designing with the TLV5617A, ensure that the reference voltage is stable and bypassed with a 0.1 µF capacitor. The power supply should be decoupled with a 1 µF capacitor close to the VDD pin. The serial clock frequency should not exceed 20 MHz to maintain reliable communication.
TLV5627IPW - 8-Bit Quad DAC, Serial, TSSOP-16 | Texas Instruments
The Texas Instruments TLV5627IPW is a quad-channel, 8-bit voltage-output digital-to-analog converter (DAC) with a flexible 4-wire serial interface, packaged in a 16-pin TSSOP (PW) and operating from a 2.7V to 5.5V supply. Each of the four DAC channels features programmable settling time of either 2.5 µs (fast mode) or 8.5 µs (slow mode) and supports a 107 kSPS update rate, enabling both precision setpoint generation and waveform synthesis from a single chip. A digital-to-analog converter (DAC) is a mixed-signal integrated circuit that converts a digital codeword into a precision analog voltage or current; an 8-bit quad DAC like the TLV5627 delivers four such converters on one die with a shared digital interface, sitting within the broader hierarchy of converter ICs > data converters > signal chain > mixed-signal semiconductors. Unlike audio DACs that target continuous high-rate streaming, the TLV5627 is an industrial/multi-channel "set DAC" intended for bias voltages, trim references, programmable gain stages, and actuator control loops where four independent low-bandwidth analog outputs are required. Key features include a glueless serial interface compatible with TMS320 DSP, SPI, QSPI, and Microwire ports, an on-chip reference input buffer, hardware and software-controlled power-down modes that cut consumption to a few milliwatts, and guaranteed monotonic output over the full -40C to +85C industrial temperature range. The four outputs share a common DAC reference, but each channel can be powered down independently for further energy savings. Internally, the TLV5627 uses a resistor-string architecture with an output buffer amplifier per channel, providing low output impedance and the ability to drive 2 kohm loads directly. The dual-supply design separates the digital and analog domains (separate AVDD and DVDD pins), which is critical for noise-sensitive applications where digital switching transients must be isolated from the analog outputs. Typical applications include industrial process control (PLC analog outputs), programmable sensor excitation, digital offset and gain trimming, four-channel waveform or bias generation in test & measurement, motor and valve control loops, and audio tone/signal generation where mid-fidelity is acceptable. When designing with this device, ensure the AGND and DGND pins are joined at a single low-impedance point near the IC to prevent digital return currents from corrupting analog output accuracy. The reference input must be driven from a low-noise source, and the unused DAC outputs can be left open or tied to a defined voltage. Programming model: load data through the serial port (DIN, SCLK, FS) per the TI TLV5627 datasheet timing diagram. This page consolidates real-time distributor pricing, drop-in compatible alternatives, and practical PCB/design notes beyond what the manufacturer datasheet alone provides.
TLV5734PAGG4 - Triple 8-Bit 30MSPS ADC for YUV/RGB Video | TI
The Texas Instruments TLV5734PAGG4 is a triple-channel 8-bit 30 MSPS analog-to-digital converter (ADC) with integrated high-precision input clamps, optimized for digitizing YUV/RGB video signals. Housed in a 64-pin TQFP (PAG) package, the device operates from a single 3.3 V supply and features a parallel CMOS digital interface. According to the manufacturer datasheet, the device provides three simultaneous 8-bit conversions at sample rates up to 30 MSPS, with on-chip 3-channel sampling, programmable gain, and clamp circuitry designed specifically to interface directly to DC-coupled video sources such as RGB/YPbPr component video or Y/C composite video. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltage levels and converts them into discrete digital codes at a defined sample rate, enabling downstream processing in DSPs, ASICs, or FPGAs. Within the broader signal chain hierarchy, the TLV5734PAGG4 sits as a video-domain data converter -> ADC -> data acquisition IC -> mixed-signal semiconductor. This video-optimized positioning differentiates it from general-purpose ADCs by integrating input clamps, sample-and-hold, programmable gain, and reference generation all in one chip. Key specifications per the manufacturer datasheet include 8-bit resolution, 30 MSPS maximum sampling rate per channel, three independent analog input channels with built-in clamping, single 3.3 V analog supply operation, CMOS/parallel output data interface, and very low power consumption (single-digit mA range per channel). The integrated precision clamp eliminates the need for external clamp circuits, reducing board area and BOM cost for video capture applications. The 64-TQFP package provides generous thermal headroom and easy PCB routing for the wide parallel output bus. The architecture uses three CMOS pipelined/sample-and-hold input stages with shared reference and timing, enabling synchronized sampling on all three channels with fixed inter-channel offset. Inputs accept standard video levels (0.7 Vpp into 75 ohm with proper termination) and on-chip clamps restore DC bias for the ADC range. The single 3.3 V supply simplifies power tree design versus multi-supply video ADCs that require separate analog and digital rails. Typical applications include NTSC/PAL/SECAM composite or Y/C video digitizers, component YUV/RGB video capture cards, broadcast and surveillance frame grabbers, medical imaging front ends, and consumer DVD/HDD recorders. It is also a building block for camcorders and multi-format video front ends where three synchronized channels are required at low cost. When designing with the TLV5734PAGG4, provide a clean 3.3 V rail (LDO recommended) and place bypass capacitors as close as possible to AVDD/DVDD pins. Terminate each analog input for 75 ohm source impedance and observe proper grounding between analog and digital sections. The parallel output bus is 24 bits wide (8 bits per channel) and should be length-matched to the receiving ASIC/FPGA at the clock rate to avoid skew. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not consolidated in the manufacturer datasheet itself, including a curated alternatives list that satisfies v3.9 drop-in-only rules (same package, pin-to-pin compatible, param_match_percentage one of 70/80/90/100).
TS7003ITD833 - 12-Bit 300ksps SAR ADC, 2.5V Ref, TDFN-8 | Silicon Labs
The Silicon Labs TS7003ITD833 is a 12-bit, 300 ksps successive-approximation analog-to-digital converter (ADC) with a single-ended single-channel input, integrated +2.5V reference, and a high-speed serial digital interface, packaged in an 8-pin TDFN (3x3 mm) with exposed pad for thermal and ground integrity. Designed for single-supply operation from +2.7V to +3.6V, it draws less than 1 mA at full 300 ksps conversion rate. An ADC in this product category is a mixed-signal data converter that translates real-world analog voltages into discrete digital codes. The successive-approximation register (SAR) architecture family uses a binary-search algorithm with an internal track-and-hold front end, achieving a balance of speed, accuracy, and low power consumption suitable for embedded sensing, instrumentation, and process-control front-ends. This part sits within the broader hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Its integrated reference removes an external component and reduces board area, an important benefit for compact sensor-interface designs. Key features include 12-bit resolution, 300 ksps throughput, a high-bandwidth input track-and-hold amplifier, and an internal +2.5V reference. The serial interface reduces pin count compared to parallel-output ADCs, simplifying routing and host-MCU connection. Low conversion-mode power consumption and an industrial temperature range support battery-aware and factory-floor deployments alike. The TS7003ITD833 successive-approximation architecture implements a charge-redistribution DAC internally, capturing input samples on the T/H at the rising edge of CNVST and presenting results one frame later through the SPI-compatible serial port. The integrated reference and single-supply rail minimizes external component count, while the 8-pin TDFN EP package provides a low-impedance thermal/ground path that enhances noise immunity at full throughput. Typical applications include industrial process-control analog front-ends, portable battery-powered data loggers, sensor-signal digitizers, weigh-scale and load-cell readouts, and microcontroller-based instrumentation. Use it where channel count is small, sampling rate is moderate, and PCB real estate is at a premium. When designing with this ADC, place the decoupling capacitor directly between AVDD and GND, keep analog and digital ground returns separated until they join at the exposed pad, and respect the tACQ acquisition-time timing parameter when writing firmware. Driving the analog input from a low-impedance buffer maintains data-sheet linearity at high source resistances. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet to help procurement and design engineers evaluate the TS7003ITD833 for new designs and second-source risk mitigation.
TSA1005-40IFT - 10-Bit 40MSPS Dual ADC | STMicroelectronics
The STMicroelectronics TSA1005-40IFT is a dual-channel, 10-bit resolution analog-to-digital converter (ADC) based on a pipelined architecture, sampling up to 40 MSPS in a 48-pin TQFP (7x7 mm) package. It uses a 0.25 µm deep sub-micron CMOS process, operates from a single 2.5 V analog supply, and supports an independent 2.5 V or 3.3 V CMOS output supply. A pipelined ADC is a high-speed converter architecture that resolves an analog input across multiple cascaded low-resolution stages, each driving a sample-and-hold amplifier and a flash sub-ADC. The pipeline allows new conversions to begin every clock cycle, achieving sample rates well above 100 MSPS while keeping per-stage hardware compact. Pipelined ADCs sit within the broader taxonomy: data converter -> ADC -> high-speed ADC -> pipelined ADC -> integrated circuit -> semiconductor. The TSA1005 belongs to a category often called "baseband IF sampling ADCs," used when analog signals need to be digitized near the antenna or sensor for downstream DSP. Key specifications include 1 GHz analog input bandwidth, an integrated track-and-hold amplifier per channel, common clocking for synchronous dual-channel sampling, and a multiplexed digital output mode. The device targets applications needing a low noise floor and high SFDR; SFDR (Spurious-Free Dynamic Range) measures how far the largest spurious tone sits below the fundamental when digitizing a pure sine wave, with higher values meaning cleaner spectra. The TSA1005 is engineered for very low noise floor, high SFDR, and good channel-to-channel isolation. Typical applications include medical ultrasound imaging, professional video processing, IF (intermediate frequency) sampling for communications receivers, instrumentation, and industrial non-destructive testing. Each application relies on the part's combination of 10-bit resolution at video-grade sample rates and dual-channel synchronous capture. When designing with this part, decouple both the 2.5 V analog and 2.5/3.3 V digital rails with 100 nF ceramic capacitors placed as close as possible to each supply pin. Route the analog inputs as 50 Ω controlled-impedance traces with the analog ground plane isolated from the digital return to minimize coupling. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical PCB layout notes not found in the manufacturer datasheet alone. Information current as of 2026-10-15.
TSA1203IF - Dual 12-bit 40MSPS ADC | STMicroelectronics
The STMicroelectronics TSA1203IF is a dual-channel, 12-bit, 40 MSPS analog-to-digital converter fabricated in a mainstream 0.25 µm CMOS process, housed in a 48-pin TQFP (7x7 mm) package. It integrates two simultaneous sample-and-hold amplifiers, a 1 GHz analog input bandwidth, and a built-in reference voltage, dissipating 230 mW at 40 Msps from a single 2.5 V supply. The CMOS output stage can be driven from an independent 2.5 V or 3.3 V rail, simplifying interfacing to both legacy and modern FPGA/ASIC logic families. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a continuous-time, continuous-amplitude analog input into a discrete-time, discrete-amplitude digital code. Pipeline ADCs such as the TSA1203IF use a multi-stage switched-capacitor architecture to achieve high sampling rates while keeping per-stage power and die area modest, sitting within the broader hierarchy of data converters -> ADC -> high-speed pipeline ADC -> semiconductor. Dual-channel variants like this one are favored for diversity receivers, I/Q baseband sampling, and simultaneous multi-antenna digital beamforming because the two channels are sampled on a common clock edge, eliminating channel-to-channel skew. Key features include 1 GHz analog input bandwidth, SFDR of -68.3 dBc at 10 MHz input, multiplexed outputs for reduced pin count, common clocking between channels, and pin-to-pin compatibility with the dual 10-bit 20/40 MSPS TSA1005-20/40 and the dual 12-bit 20 MSPS TSA1204. The pipelined architecture combined with digital error correction yields clean 12-bit outputs at full clock rate without requiring complex external calibration at room temperature. Typical applications include cellular base station receivers, IF sampling for software-defined radio, medical imaging front-ends, and industrial ultrasound beamformers. The integrated reference and dual independent input channels also suit multi-channel data-acquisition cards for test and measurement instrumentation. When designing with this part, ensure the analog and digital grounds are joined only at a single point near the exposed pad, and that the analog supply is decoupled with both 0.1 µF ceramic and 10 µF bulk capacitance within 5 mm of the supply pins.
TSA1204IFT - 12-Bit 20MSPS Dual-Channel ADC | STMicroelectronics
The STMicroelectronics TSA1204IFT is a 12-bit resolution, dual-channel pipelined Analog-to-Digital Converter sampling up to 20 MSPS, packaged in a 48-pin TQFP (7x7 mm). The device operates from a single 2.5 V analog supply with an independent 2.5 V/3.3 V CMOS output stage supply, consuming only 95 mW per channel at 20 MSPS and scaling down adaptively at lower sampling rates. An Analog-to-Digital Converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a specified sampling rate. Dual-channel pipelined ADCs belong to the broader hierarchy of data converter IC -> mixed-signal IC -> semiconductor, and they occupy the performance tier between successive-approximation (SAR) converters (slow, low-power, <5 MSPS) and high-speed flash converters (very fast, very high power). The TSA1204IFT targets moderate-bandwidth multi-channel systems where engineers need two synchronized channels without the cost of two discrete ADCs. Key features include a 1 GHz analog input bandwidth, an integrated Track-and-Hold amplifier, 11.2-bit effective number of bits (ENOB) at the Nyquist input frequency, and -81.5 dBc spurious-free dynamic range (SFDR) at Nyquist. The 0.25 micrometer CMOS process enables adaptive power consumption scaling from 0.5 MSPS to 20 MSPS, allowing the part to drop to lower power in standby. The CMOS outputs are pin-selectable between 2.5 V and 3.3 V logic levels, simplifying interface to FPGAs, ASICs, or microcontrollers in mixed-voltage systems. Typical applications include dual-channel digital oscilloscopes, intermediate-frequency (IF) signal processing in communications receivers, ultrasound imaging front-ends, and high-speed industrial data acquisition. The dual channel allows simultaneous sampling of in-phase and quadrature (I/Q) baseband signals, or two channels of a multi-channel instrumentation system. When designing with the TSA1204IFT, place the analog and digital ground returns on a split ground plane joined under the ADC, use wide PCB traces for the analog supply pins, and decouple each supply pin with 100 nF and 10 uF capacitors placed as close as possible to the device. The exposed pad of the TQFP should be soldered to a ground plane for thermal and electrical performance. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not collected in any single manufacturer datasheet revision, giving engineers a one-stop reference for sourcing and second-sourcing the TSA1204IFT.
TSA1401IF - 14-bit 20MSPS 85mW ADC | STMicroelectronics
The STMicroelectronics TSA1401IF is a 14-bit, 20 MSPS pipelined analog-to-digital converter that consumes only 85 mW at full sampling rate. Housed in a 48-pin TQFP (7x7 mm) package, the part targets low-power imaging and instrumentation applications where conventional 14-bit ADCs exceed the system thermal budget. According to the STMicroelectronics datasheet, the TSA1401IF implements ST's OPTIMWATT architecture to dynamically scale internal bias currents with clock rate, enabling designers to lower the sampling clock for slower channels and reduce overall system power. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that quantizes a continuous-time analog input into a discrete N-bit binary code at a programmable sample rate. TSA1401IF sits in the high-speed, mid-resolution segment of the ADC taxonomy (ADC -> pipelined ADC -> high-speed ADC -> data converter -> mixed-signal IC). Pipelined ADCs use multiple low-resolution flash stages interleaved with residue gain and digital correction to achieve both high conversion rate and moderate resolution; this architecture dominates the 10-100 MSPS / 10-14 bit space used in CCD imaging, ultrasound front ends, and digital oscilloscope channels. Key specifications include 14-bit resolution, 20 MSPS maximum sample rate, 85 mW typical power dissipation at full speed, single 5 V analog supply, single +3 V to +5 V digital supply, 48-pin TQFP (7x7 mm) package, industrial temperature range (-40 C to +85 C), and an external reference input. The pipelined converter includes self-calibrated digital error correction that typically holds DNL within 0.5 LSB and INL within 1.0 LSB across the industrial temperature range. Differential analog inputs are AC-coupled through on-chip clamp protection, supporting full-scale ranges from 1 Vp-p to 2 Vp-p driven by op-amp or transformer front ends. Typical applications include high-end infrared imaging for surveillance and thermography, X-ray medical imaging front ends, professional CCD camera front ends for broadcast and industrial vision, document scanners and digital copiers, and test instrumentation including digital storage oscilloscopes and arbitrary waveform recorders. Designers value the TSA1401IF in battery-powered portable imaging systems where total BOM power directly limits field runtime. When designing with the TSA1401IF, the analog input must be driven from a low-impedance differential source; designers typically use a transformer (for single-ended to differential conversion) or a fully-differential op-amp such as the THS4503. Decoupling must include 10 uF tantalum plus 100 nF ceramic on each supply pin, placed within 5 mm of the package. The clock line should be routed with 50 ohm controlled impedance and kept away from analog signal traces. This page synthesizes distributor pricing, identical-footprint drop-in alternatives from the same STMicroelectronics family, and practical layout notes that complement the official datasheet.
TSA7887ARMZ - 12-Bit 125ksps 2-Ch SAR ADC | Silicon Labs
The Silicon Labs TSA7887ARMZ is a 12-bit, 125 ksps, 2-channel successive-approximation register (SAR) analog-to-digital converter with a serial SPI/QSPI/MICROWIRE-compatible output, an internal 2.5V reference, and an 8-pin MSOP package. Originally developed by Touchstone Semiconductor (later acquired and second-sourced by Silicon Labs), the device operates from a 2.7V to 5.25V analog supply and is targeted at low-power instrumentation that demands sub-microamp standby current and 12-bit true conversion precision. An SAR ADC (successive-approximation-register analog-to-digital converter) is a type of data converter that uses a binary-search algorithm against an internal capacitive DAC to resolve an analog input one bit per conversion clock cycle. It belongs to the broad family of analog-to-digital converters (ADCs), which itself is part of the data-converter hierarchy inside mixed-signal and signal-chain integrated circuits. The SAR architecture is favored over delta-sigma and pipeline ADCs when low-latency deterministic conversion, small package size, and moderate sample rates (tens to hundreds of ksps) are required, particularly in multiplexed multi-channel systems. Key features of the TSA7887ARMZ include an internal 2.5V reference (selectable externally via the REF pin), a 2-channel analog input multiplexer, true 12-bit performance with no missing codes, a 125 ksps maximum throughput, low power dissipation (typically under 2.5 mW at 3V/100 ksps), and automatic power-down between conversions that drops supply current below 1 microampere. The device uses an external clock for the serial interface and supports both unipolar single-ended and pseudo-differential input configurations. The device leverages a charge-redistribution SAR core with input transient suppression and an automatic input common-mode settling window, which makes it tolerant of source-impedance variations when channels are switched. Combined with the internal precision reference, this means the TSA7887ARMZ can replace an external ADC + reference + op-amp buffer chain in many space-constrained designs. Typical applications include portable and battery-powered data loggers, industrial process-control sensor front-ends (thermocouple, RTD, strain-gauge bridges), handheld instrumentation, and multiplexed 4-20 mA loop monitors. Designers also use it in optical sensor modules and consumer battery chargers where periodic current/voltage telemetry is required. When designing with this part, size the input RC network and reference bypass capacitors per the datasheet's application circuit - inadequate decoupling is the most common cause of last-2-LSB noise and gain drift in SAR circuits. Consider the MAX1276CTC+ from Maxim's family as a drop-in 8-pin MSOP alternative if higher conversion speed is needed. This page synthesizes distributor pricing, drop-in MSOP-8 alternatives, and practical design notes not found in the manufacturer datasheet alone.
TSA7887ARMZ-REEL - 12-bit 125ksps 2-ch SAR ADC | Silicon Labs
The Silicon Labs TSA7887ARMZ-REEL is a 12-bit, 125 ksps, 2-channel successive-approximation-register (SAR) analog-to-digital converter housed in an 8-pin MSOP package with a single +2.7V to +5.25V supply. The 'RMZ' suffix indicates the MSOP-8 (RM) tape-and-reel (REEL) packaging variant. Originally designed by Touchstone Semiconductor as a pin-compatible second source for the ADI AD7887, the part features an internal +2.5V reference, internal wideband track-and-hold, and serial I/O compatible with SPI, MICROWIRE, QSPI, and DSP ports. Typical supply current is 0.85 mA at full throughput, qualifying the part as a micropower converter for battery and loop-powered systems. A SAR ADC is a successive-approximation-register analog-to-digital converter, a converter topology that uses a binary-search algorithm and a capacitive charge-redistribution DAC to resolve each conversion in N clock cycles for an N-bit result. SAR converters sit in the data-converter hierarchy between flash converters (fastest, lowest resolution) and sigma-delta converters (highest resolution, slowest). They are valued for deterministic latency, low power consumption, and the ability to drive them directly from a microcontroller or DSP serial port without an external reference or high-speed clock. Key features include a 500 ns input track-and-hold acquisition time, an internal +2.5V reference that eliminates external reference components, and a single-ended analog input structure that supports one or two channels multiplexed to the ADC core. Throughput scales with the external serial clock up to 125 ksps at 2 MHz SCLK. The wide supply range allows direct interfacing to 3.3V and 5V microcontrollers, while the small MSOP-8 footprint suits space-constrained sensor readouts and portable instrumentation. Typical applications include transducer and sensor signal conditioning, battery-powered data loggers, industrial process control loops with 4-20 mA interfaces, and portable medical or instrumentation front-ends. The combination of low power, internal reference, and small footprint also suits loop-powered 4-20 mA smart transmitters where every milliwatt and square millimeter matters. When designing with this device, ensure the analog input stays within the input common-mode range specified by the supply, and add a small RC anti-alias filter on each input to limit out-of-band noise folding into the conversion result.
TSA7887ARZ - 12-bit 125ksps 2-ch SAR ADC | Silicon Labs SOIC-8
The Silicon Labs TSA7887ARZ is a micropower, 2-channel, 125-ksps, serial-output 12-bit successive-approximation analog-to-digital converter housed in an 8-pin SOIC (RZ) package. It integrates a precision 2.5V internal reference, supports a single 2.7V to 5.25V analog supply, and consumes only 3.2 mW at 125 ksps with full power-down modes reducing quiescent current to sub-microamp levels. The part accepts true bipolar input ranges via flexible reference configuration. An ADC (analog-to-digital converter) is a data-acquisition integrated circuit that samples continuous analog voltages and converts each sample into a discrete digital code for processing by a microcontroller, DSP, or FPGA. Successive-approximation-register (SAR) ADCs use a binary-search algorithm against a precision DAC and reference to resolve one bit per clock cycle, achieving a deterministic conversion time of N cycles for N-bit resolution. This conversion topology sits in the broader hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. SAR ADCs are prized for low latency, deterministic behavior, and absence of pipeline-latency artifacts. Key features include 12-bit resolution with no missing codes, an integrated 2.5V reference, an SPI-/QSPI-/MICROWIRE-compatible serial interface, true-differential analog inputs, software-configurable unipolar/bipolar input ranges, and a hardware-power-down pin. The internal reference can be overdriven with an external source, simplifying ratiometric measurements such as bridge-sensor readings. An on-chip oscillator eliminates the need for an external clock source in cost-sensitive designs. Architecturally, the TSA7887ARZ uses a charge-balancing switched-capacitor DAC front end that converts the input voltage into a digital code across 12 SAR clock cycles. The auto-calibration cycle corrects offset and gain errors on every conversion, eliminating drift across temperature and supply variations. Serial data is clocked out MSB-first and conforms to standard SPI modes, allowing direct connection to most modern microcontrollers without glue logic. Typical applications include portable instrumentation, battery-powered data loggers, industrial process-control loops, sensor conditioning modules, and panel-meter front ends. The low power draw makes it particularly attractive for solar- or energy-harvesting systems where average current budget is critical. The integrated reference and 2-channel mux further reduce total BOM and PCB area in compact designs. When designing with this part, ensure the analog supply is decoupled with a 1uF ceramic plus a 10uF bulk capacitor placed within 5 mm of the AVDD pin. Reference-pin decoupling is equally critical - a 0.1uF ceramic directly across REF should be used. Avoid switching digital traces under the analog front end to preserve SNR. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
TSA7887ARZ-REEL - 12-bit 125ksps 2-ch SAR ADC SOIC-8 | Silicon Labs
The Silicon Labs TSA7887ARZ-REEL is a 2-channel, 12-bit successive-approximation analog-to-digital converter (SAR ADC) with a 125 ksps throughput rate and serial SPI-compatible output, housed in an 8-pin SOIC package. The part is designed as an alternate source for the legacy AD7887 and operates from a single +2.7 V to +5.25 V supply while drawing only 0.85 mA typical supply current, supporting micropower applications. An integrated 2.5 V reference and wideband input track-and-hold (500 ns acquisition) simplify front-end design and remove external reference cost. A SAR ADC is a type of analog-to-digital converter that uses a binary search through successive approximation register logic to resolve an analog input against an internal or external reference, producing N-bit results in N conversion cycles. SAR ADCs excel at medium-to-high resolution (12-18 bit) sampling at moderate speeds (10 ksps to 10 Msps) without the pipeline latency of higher-speed flash or pipelined architectures, making them ideal for multiplexed multi-channel data acquisition systems. Within the data-converter hierarchy, the TSA7887ARZ-REEL sits as a precision ADC -> data converter -> signal chain IC -> mixed-signal semiconductor, combining analog input conditioning, reference generation, and digital serial interface on a single die. Key features include a 125 ksps maximum sampling rate, two single-ended analog input channels multiplexed into one ADC core, an internal 2.5 V reference, a low 0.85 mA supply current, a wide input bandwidth track-and-hold (500 ns), and a serial interface compatible with SPI/QSPI/MICROWIRE. The device accepts bipolar-input-capable front end via simple resistor networks and provides an external reference option when system-level drift compensation is required. The 8-pin SOIC footprint supports standard surface-mount assembly flows. Architecturally, the TSA7887ARZ-REEL uses a charge-redistribution DAC array with successive-approximation register logic clocked from an external serial clock up to 2 MHz. The wideband track-and-hold preserves signal fidelity above the Nyquist limit of the 125 ksps sampling rate, while the integrated reference and input MUX eliminate the external analog conditioning typically required for discrete ADC designs. The serial output reduces pin count versus parallel-output ADCs and simplifies galvanic isolation in industrial systems. Typical applications include portable battery-powered instrumentation, industrial process-control loop monitoring, multi-channel data-logger front ends, sensor-signal conditioning for strain-gauge and thermocouple inputs, and touch-screen / resistive-position decoder interfaces. The low 0.85 mA supply current also suits remote or solar-powered sensor nodes. Where higher throughput is needed, the part's SPI-compatible daisy-chain capability lets two devices share a single serial port. When designing with this device, drive the analog inputs from low-impedance buffers (<= 50 ohm source impedance) to avoid conversion errors caused by the kick-back charge of the internal CDAC array. Bypass VDD with a 0.1 uF ceramic plus 10 uF tantalum placed within 5 mm of the supply pin, and provide a clean analog ground return to keep the integrated reference stable. The throughput scales linearly with external SCLK; a 2 MHz SCLK yields the rated 125 ksps. Note that the TSA7887ARZ-REEL is currently listed as obsolete by Silicon Labs (last-time-buy status), so long-life designs should consider the newer AD7887SRZ-EP equivalent. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.