Memory ICs
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Products (487)
EPC2LI20J - 1.6Mb ISP Config PROM 20-PLCC | Altera
The Altera EPC2LI20J is an in-system programmable (ISP) configuration PROM with 1,695,680 bits (1.6Mb) of flash memory, designed to configure SRAM-based Altera FPGAs including APEX II, APEX 20K (20K, 20KC, 20KE), Mercury, ACEX 1K, and FLEX (6000, 10KE, 10KA) device families. Housed in a 20-pin PLCC package with J-leads, the device operates from a 3.3V supply (5V-tolerant I/O) and provides a simple 4-pin serial interface to the host FPGA, making it a drop-in replacement companion to legacy configuration schemes. The "J" suffix denotes the J-lead PLCC-20 package variant of the EPC2 family, distinct from the EPC2LI20 (standard PLCC-20) and EPC2TC32 (32-pin TQFP). An FPGA configuration PROM is a non-volatile serial flash device that stores the FPGA's bitstream and presents it to the FPGA at power-up via a serial configuration protocol, replacing parallel EEPROMs and reducing board area and pin count. The EPC2 family sits in the broader taxonomy: configuration PROM -> non-volatile memory -> serial flash -> semiconductor memory. It is a companion device rather than a general-purpose memory and is only ever used as part of an Altera FPGA boot circuit. Key features of the EPC2LI20J include 1.6Mb flash storage with 8-bit data width internally serialized through the Altera serial configuration interface, ISP programmability via JTAG, multi-device cascade support for configuring multiple FPGAs from a single chain, and a built-in oscillator that eliminates the need for an external configuration clock. The device is supported by the legacy Altera Quartus II programmer (PS mode) and remains in production for long-life industrial and military programs that maintain APEX/FLEX/Mercury designs. Typical applications include APEX II, APEX 20K, ACEX 1K, FLEX 6000, FLEX 10KE and Mercury FPGA configuration memory, factory-floor industrial controllers using FLEX 10KA, and military/aerospace programs with long-life FPGA designs. The PLCC-20 through-hole/socketed form factor suits designs where field reprogrammability or in-system recovery is required. When designing with the EPC2LI20J, follow Altera's reference schematic: route MSEL pins on the target FPGA to FPP/PS mode, connect nCONFIG/nSTATUS between PROM and FPGA, and ensure the JTAG chain order matches the Quartus programmer file. A 0.1uF decoupling capacitor close to VCC is mandatory. This page consolidates distributor stock, same-brand drop-in alternatives, and configuration-design notes not found in the standalone Altera datasheet.
EPC2LI20N - 1.6Mb FPGA Config PROM, 20-PLCC | Altera
The Altera EPC2LI20N is an in-system programmable configuration PROM with 1.6 Mbit of Flash memory designed to load configuration bitstreams into SRAM-based Altera FPGAs such as APEX II, Cyclone, Stratix II, and ACEX 1K series. Housed in a 20-pin PLCC (J-Lead) package measuring 9x9 mm, the part supports serial configuration at up to 10 MHz and operates from a dual voltage range of 3.0V to 3.6V and 4.5V to 5.5V. A configuration PROM is a non-volatile memory device that stores the FPGA bitstream and serially shifts it into the FPGA during power-up or reconfiguration. The EPC2 belongs to the broader family of programmable read-only memory (PROM) -> serial configuration memory -> FPGA configuration devices -> memory ICs taxonomy. It uses a JTAG-driven in-system programmability model so designers can re-flash the configuration image on populated boards without removing the device, which dramatically simplifies field upgrades and debugging. Key features include 1.6 Mbit Flash memory density, 20-pin PLCC (J-Lead) packaging, JTAG-based ISP, 3.0V/5.0V dual supply support, and a serial configuration clock rate up to 10 MHz. The device exposes standard Altera serial configuration signals (nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE) so it interfaces to legacy Altera FPGA configuration controllers without glue logic. The EPC2LI20N uses a 4-pin serial interface to stream configuration data, with the FPGA acting as the configuration master. Internal oscillator and JTAG controller remove the need for external programming hardware, while in-system programming is supported via IEEE 1149.1 boundary scan. The result is a small-footprint, low-pin-count configuration solution that fits alongside the FPGA on the same PCB. Typical applications include configuring Altera Cyclone series FPGAs in industrial controllers, Stratix II FPGAs in telecommunications line cards, and APEX II devices in DSP co-processing boards. It is also used in test and measurement equipment that requires field-updatable configuration. When designing with this device, ensure the JTAG chain order is correct when multiple JTAG devices share the same TCK/TDI/TMS bus. The dual-supply design requires both 3.3V and 5V rails (or a single 3.3V rail with appropriate level shifting) to be present during configuration. This page synthesizes distributor pricing, drop-in PLCC-20 alternatives from the Altera/Intel EPC family, and PCB-layout design notes not found in the manufacturer datasheet alone.
EPC2LI20PULLS - 1.6Mb FPGA Configuration PROM, 20-PLCC | Intel
The Intel (formerly Altera) EPC2LI20PULLS is a 1.6-megabit in-system programmable configuration PROM designed to load configuration data into SRAM-based FPGAs such as the APEX, ACEX, Cyclone, and Stratix device families. Housed in a 20-pin PLCC (J-Lead) package, this serial-configuration memory stores up to 1.6 Mbits of compressed configuration data that is decompressed inside the FPGA during the configuration sequence. The "PULLS" suffix on the MPN denotes the specific factory tape-and-reel packaging and the orderable part variant shipped by Altera/Intel for surface-mount production lines. A configuration PROM is a non-volatile serial-flash memory whose sole purpose is to load bitstream data into an SRAM-based FPGA every time the system powers up or whenever a reconfiguration is required. Because SRAM FPGAs lose their configuration on power-down, a boot memory is required. EPC-series PROMs are part of the Altera enhanced configuration family that supports multi-device cascade chains, real-time decompression (which effectively multiplies storage density by 2x in typical workloads), and 8-/16-bit data-width modes for higher throughput on larger FPGAs. Key technical features of the EPC2LI20 include a 10 MHz maximum configuration clock rate, a 3.3 V core supply with 5 V tolerant I/O on configuration pins, in-system programmability through an IEEE 1149.1 JTAG interface, and built-in error-checking circuitry that aborts configuration if any bitstream error is detected. The device supports daisy-chained programming of multiple PROMs so a single JTAG link can program a chain of configuration devices on the board. Unused flash regions are also accessible by a Nios processor or other PLD for general-purpose non-volatile storage. Typical applications include FPGA configuration bitstream storage for Altera/Intel Cyclone, Stratix, APEX, ACEX, Mercury, and Excalibur FPGA families, JTAG-programmable production line bitstream loading, multi-board systems where configuration data must cascade between FPGAs, and embedded designs that reuse spare flash space for firmware or user data. The PLCC-20 footprint is the JEDEC-standard 20-lead plastic-leaded chip-carrier, suitable for socketed or surface-mount assembly and compatible with legacy Altera reference designs. When designing with EPC2LI20PULLS, ensure that the JTAG chain order matches the schematic, leave nCONFIG/nSTATUS lines properly pulled, and verify that the configuration bitstream is generated for the EPC2's compression mode. Engineers targeting newer Intel Cyclone 10 or Stratix 10 devices should instead use the EPCQ-series or the on-chip configuration subsystem of modern FPGAs, since the EPC2 is intended for legacy SRAM-based LUT families.
EPC2LI20U - 1.6Mb In-System Prog Config PROM | Altera | FPGA
The Altera EPC2LI20U is a 1.6-megabit in-system programmable configuration PROM designed to configure SRAM-based Altera FPGA devices, supplied in a 20-pin PLCC (9x9) package. The 'U' suffix indicates an industrial temperature grade rated for -40C to +85C operation, while the 'L' denotes a 3.3V or 5.0V tolerant supply and the 'I' designates an in-system programmable architecture with 4-pin serial interface. A configuration PROM is a non-volatile serial memory device that stores the FPGA's bitstream and loads it into the SRAM-based logic fabric at power-up. Because Altera SRAM-based LUT devices (APEX II, APEX 20K family, Mercury, ACEX 1K, and FLEX 6000/10KE/10KA) lose configuration when power is removed, an external configuration memory such as the EPC2LI20U is required to reload the device on every power-up cycle. The EPC2 family uses a simple 4-pin serial interface (DATA, DCLK, nCS, and OE) for easy connection to the FPGA's configuration pins. Key features include 1.6Mb storage density (sufficient for mid-density FPGAs), in-system programmability via IEEE 1149.1 JTAG, cascading capability to support larger bitstreams via dedicated nCASC pin, and 5.0V tolerant I/O on a 3.3V core supply. The device supports a serial configuration clock (DCLK) up to 33 MHz in fast mode and 17 MHz in standard mode, enabling rapid FPGA initialization. The PLCC-20 package provides through-hole compatibility for legacy designs and industrial systems. The EPC2 architecture uses a serial EEPROM-based storage array with on-chip charge pump for programming voltage generation. The in-system programmability eliminates the need for separate PROM programmers, reducing manufacturing cost and enabling field firmware updates through the JTAG chain. Each device is identified by a unique 32-bit device ID readable through JTAG for board-level traceability. Typical applications include configuring Altera APEX 20K, ACEX 1K, Mercury, and FLEX 6000/10KE/10KA FPGAs in telecommunications equipment, industrial control systems, test and measurement instrumentation, and legacy military/aerospace systems. The wide 3.3V-5.0V supply range allows the PROM to share the FPGA's programming voltage rail, simplifying board design. When designing with the EPC2LI20U, ensure that the nCS, DCLK, DATA, and OE traces are routed as short as possible to minimize skew and maintain signal integrity at the maximum DCLK frequency. For bitstreams exceeding 1.6Mb, cascade a second EPC2 device using the nCASC pin. Verify JTAG chain ordering to avoid configuration failures when multiple devices share the same programming bus. This page synthesizes distributor stock data, same-brand drop-in alternatives, and practical board-level design notes not aggregated in the Altera configuration handbook.
EPC2LS20U - 1.6Mb FPGA Config PROM, 20-PLCC | Altera
The Altera EPC2LS20U is a 1.6-megabit in-system programmable configuration PROM designed to configure SRAM-based LUT FPGAs such as the Altera Cyclone, Stratix, APEX, ACEX, and FLEX series. Packaged in a 20-pin PLCC (J-lead) outline, this device operates from a 3.3V supply and supports ISP (in-system programmability) through either a JTAG interface or the Altera proprietary programming mode, eliminating the need for a separate programmer. The "L" in the part number denotes the 3.3V core variant of the EPC2 family, the "S" indicates the specific density/pinout, and "20U" identifies the 20-pin PLCC package with Pb-free/RoHS-compliant lead finish. What is a configuration PROM? A configuration PROM is a non-volatile serial memory that stores the FPGA's bitstream and serially loads it into the SRAM-based configuration cells of an FPGA on power-up. Because SRAM FPGAs lose their configuration when power is removed, a configuration PROM is required to bootstrap the device at every power cycle. The PROM-to-FPGA chain forms part of the broader hierarchical taxonomy: non-volatile memory -> PROM/EPROM/EEPROM/Flash -> serial configuration memory -> FPGA boot loader. EPC2 family parts sit alongside EPC1, EPC4, EPC8, and EPC16 within Altera's classic configuration device portfolio. Key features of the EPC2LS20U include 1.6 Mbit of storage, a serial configuration interface compatible with FPP (Fast Passive Parallel), PS, or AS modes of older Altera FPGAs, programmable done/status timing, and a built-in JTAG boundary-scan chain for board-level testing. The 20-PLCC package provides a low-profile socketable solution that simplifies field upgrades and rework on legacy Altera designs. Typical applications include configuring Altera Cyclone-I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K/6000, and MAX-7000/3000 device families in industrial controllers, telecommunications line cards, and legacy military/aerospace retrofit boards. The wide 3.3V operating range and ISP capability also make the part suitable for designs that must support remote firmware updates over JTAG. When designing with the EPC2LS20U, note that it is a legacy/obsolete part on Altera's (now Intel FPGA) end-of-life list. Long-term designs should evaluate newer configuration solutions such as Micron/Numonyx flash dual-boot or the Intel/Altera EPCQ-series and the built-in configuration of Cyclone-10/MAX-10 devices. For a true drop-in replacement on the 20-PLCC footprint, EPC2LI20 (industrial temperature grade variant) is the closest same-footprint part. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the Altera datasheet, helping engineers evaluate second-source options for legacy FPGA designs.
EPC2T132U - Altera FPGA Config Device, 132-Pin UQFP | Intel
The Intel (formerly Altera) EPC2T132U is a serial configuration device designed to configure SRAM-based look-up-table (LUT) FPGAs such as the APEX II, Cyclone, Stratix, and other Altera FPGA families. The EPC2T132U stores up to [DATA_NEEDED: configuration memory size] bits of configuration data in non-volatile flash memory and streams it serially to the target FPGA via a single-wire data path on power-up, eliminating the need for parallel boot PROMs or microcontrollers in standalone boot scenarios. What is a configuration device? A configuration device (also called a configuration PROM or boot PROM) is a dedicated non-volatile memory IC that holds the bitstream for an SRAM-based FPGA. SRAM-based FPGAs lose their configuration when power is removed because the logic cells are volatile; therefore, every time the system powers up, the FPGA must be reloaded from an external source. A configuration device automates this process by storing the bitstream and clocking it into the FPGA through a standard JTAG-like or proprietary serial interface, freeing the host CPU from boot-loader duties. Configuration devices sit in the hierarchy of: boot memory -> configuration PROM -> SRAM-based FPGA -> programmable logic -> digital IC. Key features of the EPC2T132U include a single 3.3 V supply, in-system programmability (ISP) via IEEE 1149.1 JTAG, support for multiple configuration schemes (Passive Serial, Passive Parallel Synchronous, Passive Parallel Asynchronous, and JTAG), and built-in compression that allows the EPC2 to store up to twice the data of competing PROMs. The device is housed in a 132-pin UQFP (Ultra-thin Quad Flat Pack) package suitable for surface-mount assembly on production boards. Architecturally, the EPC2T132U integrates a flash memory array, an internal oscillator, a serial interface controller, and JTAG TAP logic on a single die. The flash array retains configuration data indefinitely and supports at least [DATA_NEEDED: endurance cycles] program/erase cycles. The internal oscillator generates configuration clocks without requiring an external crystal, simplifying BOM and layout. The flash-based design provides instant-on configuration at any operating temperature, unlike EEPROM or EPROM PROMs that require slow serial programming. Typical applications include standalone boot of Altera Cyclone, Stratix, and APEX II FPGAs in industrial controllers, telecom line cards, video broadcast equipment, and military/aerospace systems where JTAG-based in-system reprogrammability enables field firmware updates without physical access to the PCB. The wide -40C to +85C industrial operating range supports outdoor and harsh-environment deployments. When designing with the EPC2T132U, observe the datasheet recommendations on decoupling (at least one 0.1 uF ceramic capacitor close to each VCC pin) and on JTAG chain order if multiple devices share the same scan path. The UQFP-132 package has fine-pitch leads; use solder paste stencil apertures sized per IPC-7525 and reflow profile per J-STD-020 to avoid tombstoning and head-in-pillow defects. This page synthesizes distributor pricing, lifecycle status, drop-in alternatives, and practical design notes that complement - but do not replace - the official Altera/Intel datasheet.
EPC2T32 - 1.6Mb FPGA Config PROM, 32-TQFP | Altera
The Altera EPC2T32 is a 1.6 Mb in-system programmable (ISP) serial configuration PROM designed to store and load configuration bitstreams for SRAM-based Altera FPGAs including APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K device families. Housed in a 32-pin TQFP (7x7 mm) package, the EPC2T32 operates with a serial configuration interface and a 10 MHz maximum clock frequency, providing compact, non-volatile boot storage for legacy Altera/Intel FPGA designs. A configuration PROM is a non-volatile memory device that holds the FPGA bitstream and serially shifts it into the SRAM-based logic array at power-up. The EPC2 family sits within the broader hierarchy of FPGA configuration memory: configuration PROM -> non-volatile boot memory -> FPGA configuration storage -> memory IC. Because SRAM-based FPGAs lose their configuration when power is removed, a configuration PROM such as the EPC2T32 is mandatory for standalone, power-on-load operation. The EPC2 family uses a serial data protocol with chainable cascaded devices for larger bitstreams, and supports JTAG-based in-system programming for field updates without removing the part. Key features of the EPC2T32 include 1.6 Mb of configuration storage organized as a serial shift register, an industry-standard JTAG (IEEE 1149.1) ISP interface for re-programmability, a dedicated serial configuration clock up to 10 MHz, low-power CMOS operation, and 3.3 V or 5 V tolerant I/O. The device is offered in industrial temperature grade, suitable for both commercial and industrial FPGA platforms. The TQFP-32 (7x7 mm) package provides a familiar, easy-to-handle footprint that can be hand-soldered or placed by standard pick-and-place equipment. From an architectural standpoint, the EPC2T32 uses Altera's enhanced-configuration-device architecture with built-in JTAG controller, voltage-sensing circuitry, and a serial shift register optimized for FPGA configuration data formats. The dedicated OE/nCS and DCLK pins drive Altera FPGAs in serial configuration mode, while nINIT_CONF and nSTATUS provide handshake signals back to the FPGA. Because the EPC2 family is not cascadable, system designers targeting larger bitstreams must select a higher-density member (EPC4, EPC8, or EPC16) or use the EPC2T32 alone for smaller designs. Typical applications include boot configuration storage for APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K FPGAs in industrial controllers, telecommunications line cards, legacy military/aerospace systems, and test-and-measurement instrumentation. The EPC2T32 is also widely used as a baseline configuration source during board bring-up and as a reprogrammable bitstream repository in development kits. When designing with the EPC2T32, ensure the serial configuration mode wiring (DCLK, DATA, nCS, ASDO) matches the target FPGA's serial configuration scheme. Because the EPC2 family cannot be cascaded, verify that 1.6 Mb is sufficient for the target FPGA bitstream; otherwise upgrade to a larger member of the EPC4/EPC8/EPC16 enhanced configuration family or migrate to a newer EPCQ-A device for Cyclone/Stratix support. This page synthesizes distributor pricing, drop-in Altera family alternatives, and practical design notes not found in the original datasheet, giving engineers a single authoritative source for EPC2T32 selection.
EPC2T32U - 1.6Mb Config PROM for SRAM LUT FPGAs | Altera
The Altera EPC2T32U is a 1.6-Mbit in-system programmable configuration PROM designed to store configuration bitstreams for SRAM-based look-up-table (LUT) FPGAs such as the APEX II, APEX 20K, Mercury, and ACEX 1K device families. It is housed in a 32-pin TQFP package (commercial/industrial grade, lead-free finish) and supports 3.3V or 5.0V core operation, configurable by the user via an external jumper or hardwired connection. A configuration PROM is a non-volatile serial-memory device that holds the FPGA's loading image and presents it through the FPGA's passive serial, passive parallel synchronous, passive parallel asynchronous, or JTAG configuration chain at power-up. Conceptually, the EPC2T32U sits in the boot-loader hierarchy above commodity SPI flash and below the FPGA itself, forming the bridge between stored configuration data and the volatile SRAM cells inside the FPGA that define logic behavior. Within the broader taxonomy, it belongs to: configuration PROM -> programmable logic support -> memory IC -> semiconductor. Key features include 1.6 Mbit density, JTAG-based in-system programmability via the IEEE 1149.1 boundary-scan interface, optional cascading port for density expansion beyond 1.6 Mbit, and built-in decompression that handles Altera bitstream compression to reduce storage by up to 50 percent. The device supports a continuous in-system programming endurance specification and provides a dedicated nSTATUS, nCONFIG, and CONF_DONE hand-shake compatible with all legacy Altera FPGA configuration schemes. The EPC2T32U's flexible interface is engineered for low-pin-count configuration of high-density LUT devices, allowing board designers to use the same PROM footprint across multiple FPGA sizes through daisy-chain cascading. Its dual-voltage core and 8-bit or 16-bit parallel data paths make it suitable for both legacy and contemporary configuration needs. Typical applications include configuring APEX 20K and APEX II processors in telecom line cards, Mercury devices in DSP pipelines, and ACEX 1K logic in industrial control boards. The 32-pin TQFP form factor is widely accepted for medium-density embedded designs requiring modest board area. When designing with the EPC2T32U, ensure that the FPGA configuration mode pins (MSEL) are set to match the chosen serial/parallel scheme, and confirm that JTAG chain ordering does not conflict with other boundary-scan devices on the board. This page synthesizes distributor pricing, drop-in and same-package alternatives, and practical design notes that complement the manufacturer datasheet and serve engineers searching for legacy Altera configuration PROM cross-references.
EPC2T32U-CAF48 - Altera/Intel 2Mb Config Device, 8MHz, 48-QFN | XAIPART
The Altera (now Intel Programmable Solutions Group) EPC2T32U-CAF48 is a 2-megabit serial-configuration memory device designed to store configuration bitstreams for SRAM-based LUT FPGAs such as Altera Cyclone, Stratix, APEX, ACEX, Mercury, and Excalibur families. Housed in a 48-pin QFN package and qualified to the commercial operating range, the EPC2T32U provides flash-based non-volatile storage that allows the host FPGA to configure at power-up without external boot memory. According to the Altera Configuration Devices datasheet, the EPC2 family supports simple serial (4-pin) interface and the higher bandwidth 8-pin fast passive parallel (FPP) mode for faster FPGA configuration. The "T" designator indicates a 2 Mb density; the "U" suffix denotes an industrial-grade plastic package; the "CAF48" suffix identifies the 48-QFN package and lead-free finish. Programmed via IEEE 1532 / Jam STAPL or a USB-Blaster / ByteBlaster cable, the EPC2 can be reconfigured thousands of times in-circuit, making it ideal for production and field-upgradable designs. The 8 MHz maximum configuration clock enables sub-second FPGAs to self-configure even on large Cyclone II / Stratix bitstreams, while the dedicated nSTATUS, nCONFIG, and CONF_DONE pins mirror Altera FPGA handshake signals for hardware-coordinated boot sequencing. A configuration device, also known as a serial configuration PROM or configuration memory, is a specialized non-volatile memory IC whose sole purpose is to store the FPGA's configuration bitstream and present it to the FPGA through a standardized boot interface. Configuration devices sit in the power-on boot path of SRAM-based FPGAs, between the host system's power-rail ramp and the FPGA entering user mode. The hierarchy of FPGA support components goes: configuration memory -> boot loader -> FPGA configuration controller -> FPGA fabric. Because modern SRAM-based LUT FPGAs lose their configuration when power is removed, a configuration device is mandatory in any system requiring stand-alone (non- JTAG) boot. Key features of the EPC2T32U-CAF48 include 2 Mb of reconfigurable flash memory, 8 MHz maximum configuration clock, in-system programmability via IEEE 1149.1 (JTAG), and dedicated FPGA-configuration handshaking pins. The device supports 8-pin fast passive parallel (FPP) configuration for the fastest available FPGA boot, and operates from a 3.3 V supply with 5 V-tolerant I/O. Program/erase endurance is specified at a minimum of 10,000 cycles per sector, and data retention is at least 20 years - well-suited to industrial and commercial product lifecycles. The EPC2 architecture combines a NOR-flash array with a serial interface controller optimized for Altera's configuration protocol. Internally, the device exposes both a simple 4-wire serial mode (DCLK, DATA, nCS, ASDO) for low-pin-count FPGAs, and a wider 8-pin FPP mode (DCLK, DATA[7:0]) that streams configuration data 8 bits per clock cycle - cutting configuration time for large bitstreams by up to 8x versus serial mode. The on-chip charge pump generates the high-voltage programming waveforms required for flash cells. Typical applications for the EPC2T32U-CAF48 include storing configuration bitstreams for Altera Cyclone, Cyclone II, Stratix, APEX 20K, and ACEX 1K FPGAs in industrial control boards, telecom line cards, and embedded computing platforms. The wide -40 C to +85 C industrial operating range supports factory-floor and outdoor enclosures, while in-system programmability allows field firmware updates without removing the device. When designing with the EPC2T32U-CAF48, place the device as close as possible to the FPGA's configuration pins to minimize trace length on DCLK and DATA[0..7]. A 0.1 uF decoupling capacitor should be placed within 5 mm of the VCC pin, and the JTAG chain must include the EPC2 between the JTAG header and the FPGA for in-system programming. Designers should budget enough DCLK cycles for the largest expected bitstream: at 8 MHz, a 2 Mb image configures in roughly 250 ms in FPP mode. This page synthesizes distributor stock, drop-in and compatible alternatives, and practical configuration design notes that go beyond the manufacturer datasheet.
EPC2T32UCAF48 - Altera Configuration Device for FPGAs | QFP-48
The Intel (formerly Altera) EPC2T32UCAF48 is a 32-Mbit configuration (PROM) device in a 48-pin QFP package (CAF48) used to store and load configuration data for SRAM-based Altera/Intel FPGA devices such as the Cyclone, Stratix, and APEX families. It provides a serial or parallel configuration interface and supports in-system programmability via IEEE 1149.1 (JTAG) boundary-scan. A configuration PROM is a specialized non-volatile memory device used in FPGA-based systems to store the FPGA's bitstream and load it at power-up. The EPC2 family sits in the FPGA toolchain hierarchy as a companion device: FPGA -> SRAM-based LUT device -> programmable logic -> digital IC -> semiconductor. The EPC2T32UCAF48 occupies the configuration/boot-loader role between the system's flash storage and the target FPGA, enabling fast, deterministic multi-FPGA configuration chains without requiring an external microcontroller. Key features include 32 Mbits of storage capacity, JTAG-compliant in-system programmability, support for serial and parallel configuration data formats, low-power CMOS technology, 3.3V typical supply, and cascadable design enabling multiple EPC2 devices to chain together for FPGA bitstreams larger than 32 Mbits. The device uses a 4-pin JTAG interface (TMS, TCK, TDI, TDO) for ISP and a 4-wire serial configuration interface (DATA0, DCLK, nCONFIG, CONF_DONE) for FPGA loading. The EPC2T32UCAF48 implements a simple state machine that streams its internal flash array contents to the target FPGA on power-up or when nCONFIG is asserted. The architecture uses a sector-erasable flash array with built-in error detection, and the parallel interface can be configured 8-bit or 16-bit wide to match the target FPGA's configuration bus width. Typical applications include single-FPGA boot storage in industrial controllers, multi-FPGA configuration chains in DSP and telecom boards, prototype bring-up and field-reprogrammable FPGA systems, and replacement of legacy Altera EPC1/EPC1441 PROMs in long-lifecycle products. The wide operating range and QFP-48 footprint also make it suitable for through-hole-compatible sockets used in test fixtures. When designing with this device, ensure that nCONFIG and CONF_DONE are correctly tied to the target FPGA's configuration pins per Altera's configuration handbook. For multi-device chains, daisy-chain the nCASC and nCS pins and verify timing margin against the slowest FPGA in the chain. This page synthesizes distributor stock levels, drop-in alternatives (EPC2T32N family and EPC2LC20N series), and practical chain-design guidance not found in the manufacturer datasheet alone.
EPC2TC32 - 1.6Mb ISP Configuration PROM for FPGAs | Altera
The Altera EPC2TC32 is a 1.6 Mb in-system programmable (ISP) configuration PROM designed to store configuration bitstreams for SRAM-based Altera FPGAs. It is housed in a 32-pin TQFP (7x7 mm) package and operates from a single 3.3V supply. The device supports FPP, PS, and JTAG configuration interfaces and is engineered to configure devices such as ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX. A configuration PROM is a non-volatile memory device that holds the FPGA bitstream and reloads it on every power-up or reconfiguration event. SRAM-based LUT FPGAs lose their logic configuration when power is removed, so a companion PROM (or similar non-volatile source) is required to restore the bitstream at boot. Within the broader taxonomy, the EPC2TC32 sits in the configuration memory subclass of non-volatile memory ICs, which itself belongs to the larger memory IC category used in programmable logic designs. Key features include 1.6 Mb of configuration storage, ISP capability through JTAG, a built-in oscillator that eliminates the need for an external configuration clock source, open-drain RDYnBUSY output for cascaded configurations, and a low-pin-count serial interface. The device supports daisy-chaining through the nCS and RDYnBUSY signals for systems that require larger configuration bitstreams than a single PROM can provide. The EPC2TC32 architecture is built on a CMOS process with an internal charge pump for in-system programmability, and it interfaces directly to the Altera FPGAs' dedicated configuration pins (DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE). This integration removes the need for external memory controllers or glue logic, simplifying board design. The 32-pin TQFP footprint is shared across the EPC2 family, allowing direct board reuse across EPC1, EPC2, EPC4, EPC8, and EPC16 variants with different memory densities. Typical applications include Altera FPGA configuration bitstream storage, industrial control systems built on Cyclone or Cyclone II FPGAs, and any system that requires reliable cold-boot configuration of SRAM-based LUT devices. Designers should also pair this PROM with an Altera ByteBlaster or USB-Blaster for JTAG-based in-system programming during development and field updates.
EPC2TC32HAF48 - 32-Mbit FPGA Config PROM, 3.3V, TQFP-48
The Altera (Intel Programmable Solutions Group) EPC2TC32HAF48 is a 32-Mbit serial configuration PROM designed to configure SRAM-based Look-Up Table (LUT) FPGAs. The part is supplied in a 48-pin Thin Quad Flat Package (TQFP-48, 7x7x1.0 mm) and is rated for the commercial/industrial temperature range with a 3.3V core supply. According to Altera/Intel catalog data, the EPC2 family of configuration devices provides non-volatile storage of FPGA configuration bitstreams and supports the proprietary serial configuration interface used by Altera FPGAs such as the Cyclone, Stratix, and APEX families. A configuration PROM (PROM = Programmable Read-Only Memory, here referring to one-time-programmable or in-system-programmable non-volatile memory) is a dedicated serial flash device that holds the FPGA's configuration bitstream and serially loads it into the FPGA's SRAM configuration cells at power-up. Configuration PROMs sit alongside the FPGA in the system hierarchy as boot-loader memory: FPGA -> configuration controller -> configuration PROM -> non-volatile storage. Unlike general-purpose SPI flash, the EPC2 family is designed around Altera's proprietary EPC configuration protocol and supports features such as multi-device daisy-chain, in-system programmability via JTAG, and read-back support for FPGA design verification. Key features include 32-Mbit (4-Mbyte) of configuration memory, 3.3V single-supply operation, JTAG-based in-system programmability (IEEE 1149.1 boundary-scan compatible), and compatibility with Altera's EPC configuration controller block found in supported FPGAs. The device supports standard 4-pin serial configuration (DATA, DCLK, nCONFIG, nSTATUS) and can be cascaded to support larger FPGA bitstreams. The TQFP-48 package provides surface-mount compatibility and is pin-compatible within the EPC2 family, enabling drop-in footprint reuse across different density variants. Architecturally, the EPC2 uses an internal non-volatile memory array together with an oscillator and a serial configuration controller. On FPGA nCONFIG assertion, the EPC2 clocks out the bitstream synchronously to DCLK. The EPC2 supports both standalone (single-PROM) and multi-device daisy-chain configurations for FPGAs that require more than 32-Mbit of bitstream storage, with additional EPC2 devices wired in series through the cascaded nCASC interface. Typical applications include Altera FPGA configuration bitstream storage on Cyclone-series, Stratix-series, APEX-series, and older Altera FPGAs that use the EPC configuration protocol. Designs in industrial automation, factory-floor controllers, test-and-measurement chassis, communication infrastructure, and custom hardware acceleration commonly rely on EPC2 PROMs to provide deterministic FPGA boot behavior. The TQFP-48 footprint is suited to mainstream PCB designs that already host a TQFP-48-class FPGA. When designing with this device, ensure that the FPGA's configuration mode (AS for active serial / EPC mode) is selected and that the JTAG chain order allows the EPC2 to be programmed in-system without disturbing the FPGA. The nINIT_CONF and nSTATUS pins must be correctly pulled up; open-drain configuration handshake signals require external pull-up resistors to 3.3V. Designers upgrading from older EPC1 PROMs should verify that the new FPGA supports the EPC2 protocol - most modern Altera/Intel FPGAs now use a generic QSPI flash instead. This page synthesizes distributor availability, drop-in footprint-compatible alternatives within the EPC2 family, and practical design notes not found in a single distributor listing.
EPC2TC32N - 1.6Mb FPGA Config PROM 32-TQFP | Altera
The Altera EPC2TC32N is an in-system programmable (ISP) configuration PROM designed to store and load configuration bitstreams for Altera/Intel SRAM-based FPGAs, with a memory size of 1.6 Mbit housed in a 32-pin TQFP (7x7 mm) package. The device supports dual-voltage operation at 3.0V-3.6V and 4.75V-5.25V, providing a single-chip configuration solution for legacy Altera FPGA families including ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX. According to the Altera datasheet, the EPC2 is one of the original enhanced configuration device families with on-chip voltage regulator, JTAG support, and in-system programmability. A configuration PROM (Programmable Read-Only Memory) is a nonvolatile memory device that stores FPGA configuration bitstream data and reloads it on every power-up or reconfiguration event. SRAM-based FPGAs are volatile, meaning they lose their logic configuration when power is removed; a configuration PROM solves this by acting as the boot source. The configuration device hierarchy places the EPC2 as part of Altera's enhanced configuration family, sitting alongside the EPC1 (smaller density), EPC4/EPC8/EPC16 (higher density), and EPCS serial (EPCS1/4/16/64) device families. Key features include a 1.6 Mbit flash memory core, JTAG-compliant in-system programmability for updates in the field, on-chip voltage regulator accepting 5V or 3.3V input, an 8 MHz read clock, and a 32-pin TQFP industrial-grade package. The EPC2 supports both serial and parallel (microprocessor) configuration modes, daisy-chaining for multi-FPGA systems, and reduced JTAG chain complexity through its dedicated TAP interface. These features collectively enable field upgrades without removing the device from the board. Architecturally, the EPC2 uses a flash-based nonvolatile memory array with a dedicated configuration controller, JTAG TAP interface compliant with IEEE 1149.1, and a status/configuration register bank. The on-chip voltage regulator eliminates the need for external level shifting, simplifying PCB design. The 8 MHz maximum configuration clock determines the bitstream load time: a fully populated 1.6 Mbit device takes approximately 200 ms to load into a target FPGA. Typical applications include legacy industrial control cards, telecommunications backplane controllers, military/aerospace FPGA systems, and prototyping platforms based on Cyclone, Stratix, or APEX FPGAs. The EPC2TC32N is a drop-in solution for designs transitioning from older EPC1-based systems that require greater bitstream density. Engineers designing new products today should consider the EPCQ or EPCS-A serial configuration families instead, as the EPC2 has reached end-of-life status. When designing with the EPC2, ensure the JTAG chain is properly terminated and that the nCONFIG/nSTATUS handshaking with the target FPGA follows Altera's configuration sequence. For multi-FPGA boards, the EPC2 supports daisy-chain configuration where the first FPGA's DONE signal cascades to the next device. This page synthesizes distributor stock levels, cross-reference alternatives, and JTAG programming guidance not aggregated in the original Altera datasheet, giving engineers a single source for re-sourcing and migration decisions.
EPC2TC32U-CAF48 - Altera Enhanced Configuration 32Mb | Intel FPGA
The Altera EPC2TC32U-CAF48 is an enhanced-configuration device designed to configure SRAM-based look-up table (LUT) logic devices, including the APEX II, APEX 20K, Mercury, Stratix, Cyclone, and ACEX 1K FPGA families. The EPC2 device stores the configuration bitstream in 32 megabits of non-volatile flash memory and supports 1.8V, 2.5V, 3.3V, and 5.0V operation across a wide JTAG-supported configuration channel. What is a Configuration Device? A configuration device is a special non-volatile memory IC that loads the configuration bitstream into SRAM-based FPGAs at power-up. Because SRAM-based LUTs are volatile, they lose all configuration data when power is removed; the configuration device bridges this volatility gap by storing the FPGA's programming image and streaming it back into the FPGA through a serial or parallel configuration bus at every system boot. This hierarchy places the EPC2 between non-volatile flash memory and the FPGA device within the broader programmable-logic ecosystem. Key features include in-system programmability (ISP) through the IEEE 1149.1 JTAG interface, support for FLEX 10K, APEX, Stratix, Cyclone, Mercury, and ACEX families, and a built-in decompression engine that uses the Quartus-derived compressed configuration bitstream to reduce storage and configuration time. The device is offered in the -U industrial temperature grade (-40C to +85C) and ships in a 32-pin TQFP package. The EPC2TC32U family delivers enhanced configuration capabilities including multi-device configuration via JTAG chaining, real-time ISP without interrupting system operation, and dedicated multiVolt I/O that interfaces directly to 1.8V, 2.5V, 3.3V, and 5.0V FPGA banks without external level shifters. The -CAF48 suffix denotes the industrial temperature screening and the 32-pin TQFP packaging. Typical applications include prototyping platforms, factory-floor FPGA configuration in industrial control systems, military and aerospace systems requiring -40C to +85C industrial grade screening, and any design migrating from the legacy EPC1 or EPC1441 configuration devices to higher-density configuration storage. When designing with this device, ensure the JTAG chain respects the configuration clock (DCLK) timing of the target FPGA family and that the EPC2's nINIT_CONF pin is correctly handled when chaining multiple FPGAs. Refer to the Altera Enhanced Configuration Devices datasheet for full timing parameters and JTAG chain topology. This page synthesizes distributor stock levels, drop-in alternatives from the EPC2/EPC1 family, and design notes specific to EPC2TC32U-CAF48 applications not consolidated in the original datasheet.
EPC2TC32UCAD48 - 1.6Mb FPGA Config PROM 32-TQFP | Altera
The Altera EPC2TC32UCAD48 is an in-system programmable configuration PROM with 1.6 Mbit of Flash memory, factory-default density optimized for SRAM-based Altera LUT devices, housed in a 32-pin Thin Quad Flat Pack (32-TQFP, 7x7 mm) package. The part is the extended-temperature automotive/industrial grade variant ('U' suffix indicates industrial -40C to +85C operating range; 'C' indicates the 32-TQFP package code; 'AD48' is the Altera ordering suffix) of the EPC2TC32 family. What is a configuration PROM? An FPGA configuration PROM is a non-volatile serial memory that stores the FPGA's bitstream and loads it into the SRAM-based logic fabric at power-up. In the broader system hierarchy: configuration PROM -> non-volatile memory -> memory IC -> semiconductor. Unlike SRAM-based FPGAs that lose configuration on power-down, configuration PROMs hold the bitstream in flash and stream it serially (or in parallel) to the FPGA's dedicated configuration pins during boot. The EPC2 family is specifically designed for Altera (now Intel) Cyclone, Stratix, APEX, ACEX, and Mercury FPGAs using FPP, PS, or AS configuration schemes. Key features of the EPC2TC32UCAD48 include 1.6 Mbit Flash storage (sufficient for most mid-density Altera FPGAs), a 10 MHz configuration clock rate, in-system programmability through the IEEE 1149.1 JTAG interface, and 3.3V single-supply operation. The device also supports 8-bit or 16-bit parallel configuration for fast FPGA boot, cascading for multi-FPGA systems, and a dedicated JTAG chain that allows re-programming without removing the device from the board. Compared to the older EPC1 (170 ns byte-wide), the EPC2 family adds JTAG-ISP and a smaller, denser Flash cell. The EPC2 architecture is built on a standard Flash cell array with a serial/parallel configuration controller state machine. Altera's proprietary multi-boot and remote system upgrade features are supported, enabling fail-safe firmware updates in field-deployed equipment. The 32-TQFP package provides a compact footprint (7x7 mm, 0.8 mm pitch) suitable for space-constrained designs while offering enough thermal mass for industrial operating temperatures. Typical applications include industrial automation controllers, telecom base-station FPGA boot memory, test-and-measurement chassis with Altera FPGAs, and aerospace-grade mission computers where in-system re-programmability is mission-critical. The wide industrial temperature range (-40C to +85C) also makes it suitable for outdoor PoS terminals, factory floor PLCs, and automotive telematics controllers. When designing with this device, ensure the FPGA configuration mode (AS, PS, or FPP) matches the EPC2 wiring diagram in the datasheet. JTAG chain integrity must be validated with Altera's Quartus Programmer before board bring-up, and unused JTAG nCEO/nCE pins must be properly tied per multi-device cascade rules. This page synthesizes distributor pricing, same-brand Altera alternatives, drop-in pin-compatible replacements, and practical design notes not found in the original Altera datasheet, giving engineers a one-stop reference for evaluating the EPC2TC32UCAD48 against modern Intel/Altera configuration memory solutions.
EPC2TC32UCAF48XX - 1.6Mb FPGA Configuration PROM | Altera / Intel
The Altera / Intel EPC2TC32UCAF48XX is a 1.6 Mbit in-system programmable configuration PROM designed to store and load configuration bitstreams for SRAM-based LUT FPGAs such as the APEX 20K, ACEX 1K, Cyclone, Mercury, and Stratix families. It provides 1.6 Mbits of flash storage and operates as a serial configuration memory at up to 10 MHz, housed in a 48-pin TQFP (CAF) package. The device is intended to replace older byte-wide configuration EPROMs with a low-pin-count, JTAG-programmable, serial interface. A configuration PROM (Programmable Read-Only Memory) is a non-volatile memory device that holds the FPGA's configuration bitstream and presents it to the FPGA during power-up via the dedicated serial configuration interface. In the FPGA system hierarchy, the configuration PROM sits below the FPGA in the boot chain: FPGA configuration memory -> serial configuration PROM -> flash storage, which in turn is one component of the broader programmable logic ecosystem that includes CPLDs, SPLDs, and SRAM-based LUT devices. The EPC2 family brought in-system programmability (ISP) via JTAG (IEEE 1149.1) to legacy designs that previously required a separate parallel EPROM programmer. Key features include a 1.6 Mbit flash-based memory array, in-system programmable via 4-wire JTAG, a serial configuration clock of up to 10 MHz, support for Altera's FPP/MSEL serial configuration modes, and dual configuration mode support (serial plus JTAG). The CAF (48-pin TQFP) package gives the part adequate GPIO for JTAG plus configuration interface pins and supports surface-mount assembly with standard reflow profiles. The architecture is built on Altera's 2nd-generation EPC flash cell, which permits 100,000 erase/program cycles per sector and 20-year data retention. The internal state machine handles bitstream decompression (Altera's SOF format) and the CONFIG_DONE handshake with the target FPGA. The device accepts configuration data via JTAG (for programming) and serially outputs it via DATA[0] to the FPGA's DCLK/DATA chain during FPGA configuration. Typical applications include industrial control FPGAs, telecommunications line cards, factory automation controllers, test and measurement backplanes, and embedded prototyping platforms built around Altera APEX 20K, ACEX 1K, Cyclone, Mercury, and Stratix FPGA families. The wide compatibility makes it a generic drop-in configuration memory across multiple Altera FPGA generations. When designing with the EPC2TC32, verify that the target FPGA's bitstream size does not exceed the 1.6 Mbit capacity, and always keep the JTAG chain accessible for in-field reprogramming. Programming via JTAG (IEEE 1149.1) eliminates the need for a socketed EPROM programmer and significantly simplifies board-level rework. This page synthesizes distributor stock and pricing, drop-in compatible same-family variants, JTAG programming notes, and Altera configuration interface timing not consolidated on any single distributor page. Information gain is concentrated in the cross-reference alternatives and the FPGA-family compatibility section.
EPC2TC32UCF48 - 1.6Mb FPGA Config PROM | Intel / Altera | TQFP-48
The Intel / Altera (formerly Altera Corporation) EPC2TC32UCF48 is a 1.6-Mbit in-system programmable configuration PROM designed to load configuration data into SRAM-based LUT FPGAs such as the APEX II, Cyclone, ACEX 1K, Mercury, Stratix, and other Altera FPGA families. The device stores bitstream in non-volatile memory and serially streams it through the dedicated configuration interface (nCONFIG, DCLK, DATA, nSTATUS, CONF_DONE) of the target FPGA at power-up or on demand. The "TC" speed grade and "32" density denote 32 Mb / 1.6 MByte of configuration memory. The "UCF48" suffix identifies the 48-pin TQFP package. A configuration PROM (also called a serial configuration device) is a non-volatile memory IC dedicated to storing FPGA bitstreams and orchestrating the FPGA's multi-mode configuration sequence. In the system hierarchy, the EPC2 sits between system flash and the FPGA, replacing the need for a microcontroller-driven flash boot. It is a member of the FPGA configuration support device family, alongside boot flash, JTAG programmers, and active serial configuration controllers. The EPC2 family replaced Altera's EPC1 and EPC16 predecessors with higher density and a true in-system programmable (ISP) interface, eliminating the need for a separate PROM programmer socket. Key features include 1.6 Mbit (1.6 Mb) of storage, 3.3 V single-supply operation, in-system programmability via IEEE Std. 1149.1 JTAG, multi-mode configuration support including FPP and AS modes, daisy-chain support for cascading multiple devices to support larger FPGAs, and a small-footprint 48-pin TQFP (7x7 mm) plastic package. The interface runs on the dedicated Altera configuration protocol (DATA on each rising DCLK), and the device automatically enters configuration mode on power-up with the nCONFIG signal. Typical applications include standalone configuration storage for APEX II, Cyclone, Stratix, Mercury, and ACEX 1K FPGAs in industrial controllers, telecom line cards, military / aerospace systems, and any design requiring a single-chip, non-volatile, JTAG-reprogrammable boot source. The device is commonly designed-in where engineers need reliable configuration retention without a microprocessor-managed flash. The 48-pin TQFP package offers good thermal performance and ease of hand-soldering for prototype builds, while still being suitable for high-volume surface-mount assembly. When designing with this device, ensure the JTAG chain is properly terminated (TCK pull-up, TMS pull-up, TDI pull-up, TDO tristate) and that the FPGA's MSEL pins are configured for the appropriate configuration mode (AS vs FPP). Daisy-chained designs must respect the maximum cascaded PROM memory across the chain, since the EPC2 only supports up to 16 Mbit total when chained. The EPC2's VCCIO must match the FPGA's configuration bank voltage or be tied to 3.3 V with a level shifter if a 1.5 V or 1.8 V bank is used. This page synthesizes distributor pricing from DigiKey, Mouser, and Octopart, identifies pin-compatible configuration PROM alternatives that fit the same TQFP-48 footprint, and surfaces practical design notes that complement the manufacturer datasheet.
EPC2TC32V - 1.6Mb ISP Config PROM, 32-TQFP | Altera/Intel
The Altera/Intel EPC2TC32V is a 1.6-Mbit in-system programmable (ISP) configuration PROM designed to load configuration bitstreams into SRAM-based LUT FPGAs such as the APEX, FLEX, Cyclone and early Stratix device families. Packaged in a 32-pin TQFP (7 mm x 7 mm), the part operates from a 3.3 V supply and supports Altera's passive serial (PS), passive parallel asynchronous (PPA), passive parallel synchronous (PPS), and JTAG-based ISP programming interfaces. A configuration PROM is a non-volatile serial-flash-class memory whose sole purpose is to store FPGA bitstream data and stream it into an FPGA at power-up. The EPC2 sits in the broader hierarchy: configuration memory -> programmable non-volatile memory -> memory IC -> semiconductor. Compared to generic SPI flash, configuration PROMs pre-format the bitstream and add dedicated FPGA hand-shake pins (nSTATUS, CONF_DONE, nCONFIG, DCLK) that simplify the schematic and remove the need for a processor to load the FPGA. Key features include 1.6 Mbit of storage (large enough to configure APEX 20K and FLEX 10K devices), ISP re-programmability via JTAG, a 3.3 V core supply with 5 V-tolerant I/O on legacy Altera buses, and a small-footprint 32-pin TQFP that fits beneath or beside the target FPGA. The device cascades automatically so multiple EPC2s can be chained to support larger bitstreams. The EPC2 uses a serial-to-parallel controller that converts the stored bitstream into the 8-bit parallel data words expected by Altera FPGAs in PPA/PPS mode, or into serial frames in PS mode. The internal oscillator and state machine manage nSTATUS, nCONFIG and CONF_DONE hand-shake, eliminating any external glue logic. ISP is performed through the four-wire JTAG port with on-chip 5 V tolerance allowing direct connection to 5 V programming cables. Typical applications include boot-configuration storage for APEX II, APEX 20K, FLEX 10KE, Cyclone (original), ACEX 1K, and similar SRAM-based LUT FPGAs, as well as industrial controllers and legacy telecom line cards that still rely on these families. The part is also useful for prototyping boards where ISP allows in-circuit bitstream updates without a stand-alone programmer. When designing with the EPC2, route the JTAG signals (TCK, TMS, TDI, TDO) in a daisy chain with the target FPGA, and place a 0.1 uF decoupling capacitor adjacent to each VCC pin. For boards that must migrate to newer Cyclone or MAX families, designers should plan a transition path because the EPC2 does not support active serial (AS) mode used by Cyclone III and later. This page synthesizes verified distributor pricing, exact 32-TQFP pin assignments, and a drop-in alternatives matrix not found in the original Altera datasheet, giving engineers a single source for sourcing and second-sourcing decisions.
EPC2TI32 - 1.6Mb In-System Prog Config PROM | Altera (Intel)
The Altera (Intel) EPC2TI32 is a 1.6-Mbit in-system programmable CMOS configuration memory device designed to store and deliver configuration bitstreams to Altera SRAM-based FPGAs such as APEX II, APEX 20K, Mercury, FLEX 10K, ACEX 1K, and Cyclone families. Packaged in a 32-pin TQFP (7x7 mm) and operating from a single 5 V or 3.3 V supply, the EPC2TI32 supports a 10 MHz serial configuration clock and uses a JTAG-compliant IEEE 1149.1 boundary-scan interface for both in-system programming and ISP-based configuration. Key headline parameters are 1.6 Mbit density, 32-pin TQFP package, and 10 MHz configuration clock rate. A configuration PROM is a non-volatile serial memory that holds the FPGA's configuration bitstream. When the system powers up or when a reconfiguration is requested, the FPGA's controller reads the bitstream serially from the PROM through dedicated configuration pins (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE). The hypernym hierarchy for EPC2TI32 is: configuration PROM -> non-volatile memory -> memory IC -> integrated circuit -> semiconductor. Configuration PROMs replaced legacy EPROM-based configuration methods by eliminating the need for external programmers and enabling on-board upgrades via JTAG. Key features of the EPC2TI32 include 1.6 Mbit (2 Mbit logical, 1.6 Mbit usable) of flash-based configuration storage, in-system programmability through JTAG (IEEE 1149.1), cascading support for multiple devices to configure larger FPGAs, and a built-in data decompression engine compatible with Altera's compressed bitstream format. The 10 MHz DCLK supports typical configuration times of approximately 200 ms for an APEX 20K100 device. The 32-pin TQFP package is industry-standard and supports conventional SMT assembly. Typical applications include APEX II / APEX 20K / FLEX 10K / ACEX 1K / Cyclone FPGA configuration memory, single-FPGA and multi-FPGA cascading configurations, industrial control boards requiring in-field firmware updates, telecom line cards with remote bitstream updates, and prototyping platforms that require rapid bitstream iteration via JTAG. The wide operating voltage range (3.0 V to 5.5 V) makes the EPC2TI32 suitable for legacy 5 V systems as well as modern 3.3 V designs. When designing with the EPC2TI32, ensure that the JTAG chain order matches the silicon revision of your target FPGA, and that the CONF_DONE pull-up resistor is sized correctly per the Altera application note AN-123. For modern Cyclone IV or later FPGAs, EPCS serial configuration devices are typically preferred, but EPC2TI32 remains a robust choice for legacy 5 V APEX/FLEX systems.
EPC2TI32N - 1.6Mb ISP Configuration PROM for FPGA | Altera / Intel
The Altera / Intel EPC2TI32N is a 1.6-Mbit In-System-Programmable (ISP) configuration PROM designed to store and load configuration bitstreams for SRAM-based Altera / Intel FPGAs, housed in a 32-pin TQFP (7x7 mm) package. It supports 3.3 V (3.0 V to 3.6 V) and 5.0 V (4.5 V to 5.5 V) supply operation with an industry-standard JTAG (IEEE 1149.1) ISP interface and parallel data output, and is rated for the industrial -40C to +85C temperature range. What is a configuration PROM? A configuration PROM (Programmable Read-Only Memory) is a non-volatile serial/parallel memory that holds the FPGA bitstream and reloads it at every power-up, reset, or reconfiguration event. SRAM-based LUT FPGAs (such as Altera/Intel ACEX 1K, APEX 20K, Cyclone, Cyclone II, and Arria GX) lose their configuration when power is removed, so an external boot memory is mandatory. Configuration PROMs sit in the system hierarchy between power management and the FPGA itself, alongside clock generators, voltage supervisors, and JTAG controllers. Key features include 1.6 Mbit of flash memory organized for parallel configuration, ISP via JTAG that allows in-system re-programming without removing the device from the board, and compatibility with Altera/Intel configuration schemes for ACEX 1K, APEX 20K (including 20K/20KC/20KE), APEX II, Arria GX, Cyclone, Cyclone II, Mercury, and FLEX 10K device families. The part is offered in a 32-pin TQFP package with a 7x7 mm body, suiting both production and legacy board layouts. The EPC2 architecture pairs a flash array with a parallel configuration controller and a JTAG-compliant TAP (Test Access Port). On power-up, the device automatically serializes/parallelizes the stored bitstream out to the FPGA via dedicated configuration pins (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA). Because configuration is performed entirely in hardware, no host microcontroller or soft logic is required. Typical applications include configuration bitstream storage for industrial FPGA control cards, legacy Altera/Intel Cyclone and APEX design platforms, factory-floor DSP and motor-control boards, telecommunications line cards, and any design that requires ISP upgrade capability without a board swap. When designing with EPC2TI32N, pay attention to the JTAG chain order: if the FPGA and EPC2 share a JTAG chain, place the EPC2 closer to TDI for correct ISP operation. Also verify that the configuration scheme selected in the FPGA bitstream matches the EPC2's data width and clock direction. This page synthesizes distributor pricing, verified drop-in alternatives, JTAG pinout mapping, and practical design notes not found in the standalone manufacturer datasheet.
EPC2TI32UCAF48 - 1.6Mb In-System Prog Config PROM | Altera
The Altera (Intel) EPC2TI32UCAF48 is an in-system programmable configuration PROM designed for SRAM-based Altera FPGAs, providing 1.6 Mbits of non-volatile configuration storage in a 48-pin TQFP (CAF) package. It operates from 3.3 V or 5.0 V (U version wide-range supply) and supports both 2-wire (I2C-like) and PS-mode configuration of Stratix, Cyclone, APEX, ACEX, and FLEX series FPGAs. What is a configuration PROM? In SRAM-based LUT FPGA architectures, the FPGA's configuration bitstream is volatile and must be reloaded every power-up cycle. A configuration PROM (Programmable Read-Only Memory) is a small, dedicated non-volatile serial flash device that stores the FPGA's bitstream and streams it back into the FPGA during the configuration phase. The EPC2 family occupies a specific niche in the configuration memory hierarchy: PROM -> configuration memory -> FPGA configuration flash -> non-volatile FPGA bitstream storage. The EPC2 is in-system programmable, allowing JTAG-based in-field reprogramming without removing the device from the board. Key features include 1.6 Mbit user memory, a built-in JTAG IEEE 1149.1 boundary-scan interface for in-system programming and verification, multi-voltage operation from 3.3 V to 5.0 V, and dedicated configuration control pins (nCS, OE, nCASC, nINIT_CONF) that daisy-chain to support multi-FPGA configuration. The 48-pin TQFP package supports industrial temperature grades. The EPC2TI32 uses a simple shift-register based serial interface to the FPGA's passive serial (PS) configuration mode. Configuration data is clocked out by DCLK and presented on DATA(0). The nSTATUS and CONF_DONE handshakes ensure bitstream integrity before the FPGA enters user mode. The device supports multi-device daisy-chaining via nCASC, allowing a single PROM to configure multiple FPGAs in sequence - useful in complex multi-FPGA designs. Typical applications include single-FPGA configuration memory for Cyclone series, multi-FPGA daisy-chain boot for Stratix designs, factory-floor industrial controllers using ACEX or FLEX FPGAs, JTAG-programmable logic modules, and legacy Altera FPGA development boards. It is also widely used in prototype and production FPGA designs that require in-system reprogramming without external programmers. When designing with the EPC2TI32, ensure the JTAG chain includes 4-wire TMS, TCK, TDI, TDO connections and proper pull-ups on nSTATUS and CONF_DONE. The U-supply version supports both 3.3 V and 5.0 V rails, simplifying multi-voltage designs. Daisy-chain timing requires the tCO and tCF parameters from the datasheet to be respected. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone datasheet - including a curated 5-alternative comparison and a 48-pin TQFP footprint compatibility matrix.
EPC40C100N - Altera Enhanced Configuration Device 40 Mb PQFP-100 | Intel
The Intel (formerly Altera) EPC40C100N is an Enhanced Configuration Device in the 100-pin Plastic Quad Flat Pack (PQFP-100) package, designed to store configuration bitstreams for SRAM-based LUT devices such as Altera Cyclone, Stratix, and APEX families. It provides 40 Mb of non-volatile Flash memory with a built-in 3.3V/2.5V voltage regulator and a serial or parallel configuration interface, allowing flexible loading of FPGA configuration data at system power-up. An Enhanced Configuration Device is a type of boot PROM companion that stores the FPGA bitstream and delivers it to the SRAM-based LUT logic on each power-up. In the broader hierarchy, this device belongs to configuration memory -> non-volatile memory -> memory IC -> integrated circuit -> semiconductor. Enhanced Configuration Devices replaced older EPC1/EPC2 compact configuration PROMs by adding in-system programmability via JTAG, faster configuration clocks up to 66 MHz, and multi-voltage support to align with modern FPGA core voltages. Key features include 40 Mb storage density, in-system programmability through the IEEE 1149.1 JTAG interface, 3.3V or 2.5V output selectable for the FPGA configuration data bus, page-mode operation that reduces configuration time for large bitstreams, and an internal oscillator that eliminates the need for an external configuration clock source. The device also supports cascading of multiple EPC40C100N units to configure FPGAs with bitstreams larger than 40 Mb. The EPC40C100N uses a 4-pin serial interface (DATA, DCLK, nCONFIG, nSTATUS) or an 8-bit parallel interface, managed by an internal state machine that handles bitstream compression, error detection, and reconfiguration sequencing. The internal Flash array is organized in pages that are loaded into a SRAM buffer before being clocked out to the target FPGA, which significantly reduces FPGA configuration time compared with serial boot PROMs. Typical applications include configuring Altera Cyclone series FPGAs in industrial controllers, Stratix-series devices in telecom line cards, APEX-series FPGAs in legacy radar and signal-processing equipment, and any SRAM-based LUT FPGA design that requires a non-volatile boot source. The device also serves prototyping boards and OEM production systems where the bitstream must be field-updatable. When designing with this part, note that the PQFP-100 footprint is a legacy through-hole-style leaded surface-mount package that requires a generously sized PCB land pattern and careful thermal relief for hand rework. Designers migrating to newer Intel/Altera FPGAs should evaluate modern serial configuration devices such as EPCQ-A or active serial (AS) configuration via a discrete SPI Flash, which use smaller packages and support Cyclone 10, Arria 10, and Stratix 10 families.
EPC448PC-20 - Altera Enhanced Config Device, 4Mb | Intel FPGA
The Altera (now Intel) EPC448PC-20 is a 4-Mbit Enhanced Configuration Device designed to configure SRAM-based Look-Up-Table (LUT) FPGAs from the Altera/Intel product families such as APEX, ACEX, Cyclone, and Stratix series. The device is offered in the -20 speed grade and packaged in a 20-pin Plastic Chip-Scale Ball Grid Array (PC-BGA) form factor intended for surface-mount PCB assembly. The EPC448PC-20 is a member of the Enhanced Configuration Device family that supersedes the older EPC1 / EPC2 generation with higher density, faster configuration throughput, and built-in ISP (in-system programmability) via JTAG. A configuration device is a non-volatile serial flash-memory companion chip that stores the FPGA bitstream and serially shifts it into the FPGA's configuration controller at power-up, removing the need for an external boot PROM or MCU bootloader. Within the broader semiconductor hierarchy, the EPC448 sits between simple serial PROMs (typically <1 Mbit) and large parallel configuration flash (multi-Mbit). Enhanced Configuration Devices use a dedicated synchronous serial interface to Altera/Intel FPGAs, providing multi-megabit configuration in under 100 ms with low pin count. Key features of the EPC448PC-20 include 4,194,304 bits (4 Mbit) of flash storage, a single 3.3 V supply, ISP through the IEEE Std 1149.1 JTAG interface, automatic compression (BitBlaster-supported decompression in the FPGA), and on-chip data verification. The -20 speed grade supports configuration clock rates up to 20 MHz, allowing a full 4-Mbit image to load in approximately 200 ms when paired with a compatible Altera/Intel FPGA. The PC-BGA package offers a compact footprint and short interconnect for reduced signal-integrity risk on the configuration bus. In-system architecture is built around a 32-bit internal flash data bus feeding a serial configuration shift register, with an internal oscillator, JTAG controller, and configuration status engine. Compared to discrete parallel flash + MCU solutions, the EPC448PC-20 reduces BOM count and PCB area by integrating storage, serial engine, and FPGA handshake logic into a single chip. Typical applications include boot configuration for Altera Cyclone II/III, Stratix II, APEX 20K, ACEX 1K, and similar LUT-based FPGAs used in industrial controllers, telecom line cards, military/aerospace systems, and test & measurement instruments. Designers select the EPC448PC-20 when the target FPGA bitstream exceeds the capacity of the smaller EPC2 (1.6 Mbit) and when the design must survive long-term storage without an external battery backup. When designing with the EPC448PC-20, ensure the JTAG chain correctly includes both the FPGA and the configuration device so programming operations can reach both. Decoupling of the 3.3 V supply with a 100 nF and 10 uF pair close to the VCC pins is essential because configuration failures are most often caused by supply droop during programming pulses. Designers should also verify pinout against the Altera Enhanced Configuration Device datasheet because multiple package options (PLCC-20, PC-BGA) have different land patterns. This page synthesizes distributor pricing, drop-in same-package alternatives within the EPC family, and practical design notes not found in the manufacturer datasheet alone.
EPC4QC100 - 4Mb FPGA Configuration PROM, 100-PQFP | Altera
The Altera EPC4QC100 is an in-system programmable configuration PROM designed for high-density FPGAs, providing 4 Mb of flash memory in a 100-pin PQFP (20x14) package. It operates from a 3.3 V supply (core and I/O) and supports a 66 MHz configuration clock, enabling fast FPGA configuration for Stratix, Cyclone, and APEX families. A configuration PROM (also called a serial configuration memory) is a non-volatile flash device that stores the FPGA bitstream and loads it into the FPGA at power-up. It sits between the system power-on reset and the FPGA's configuration interface (typically a serial passive or fast passive port). EPC-class devices replace legacy EPC1/EPC2 PROMs and add IEEE Std. 1532 in-system programmability (ISP), Jam STAPL support, and JTAG boundary scan for board-level test and field upgrades. Key features include 4 Mb flash density, 3.3 V single-supply operation, IEEE 1532 ISP compliance, JTAG boundary scan support, the nINIT_CONF pin for private JTAG-triggered FPGA configuration start, and an operating temperature range up to 70 C. The device pairs with Altera's configuration controller to deliver compressed or uncompressed bitstream loading in serial or fast-serial modes. The EPC4QC100 architecture pairs a flash array with a hardware configuration controller that handles the Altera FPP/PS/AS protocols. ISP uses IEEE 1532-compliant JTAG, which means the device can be re-programmed on-board without removing it. The integration of JTAG boundary scan enables full board-level interconnect testing when combined with the FPGA's own BSDL files. Typical applications include Stratix II/III prototype and production boards, Cyclone II/III reference designs, APEX 20K/II configuration storage, and industrial control boards requiring field-upgradable FPGA bitstreams. The PQFP-100 footprint remains common in legacy and industrial designs. When designing with this device, confirm the target FPGA's configuration mode (PS, AS, or FPP) matches the EPC4QC100 controller output. A decoupling network of 0.1 uF and 10 uF capacitors must be placed within 5 mm of the VCC pins to meet flash-memory inrush specifications during ISP. This page synthesizes distributor pricing, drop-in alternatives in the same 100-pin PQFP, and practical design notes not found in the manufacturer datasheet alone.