10AS057K2F35I1HG vs 10AS057K2F35I2LG Comparison
Detailed side-by-side comparison of 10AS057K2F35I1HG by Intel and 10AS057K2F35I2LG by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
10AS057K2F35I1HG - Arria 10 SX SoC FPGA, 570K LE, 1152-FCBGA | Intel
10AS057K2F35I1HG ✓ Active
Specification Comparison
| Parameter | 10AS057K2F35I1HG | 10AS057K2F35I2LG |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3,820.00 | $1,545.00 |
| Device Family | Arria 10 SX SoC FPGA | — |
| Logic Elements | 570K | 570,000 |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Fabric Frequency | 1.5 GHz | — |
| User I/O Count | 396 | — |
| Package | 1152-FBGA, FC (35x35 mm) | 1152-pin FC-FBGA (F35), 35 x 35 mm |
| Speed Grade | K2 (mid) | -I2 |
| Temperature Grade | Industrial (I1: -40C to +100C) | Industrial (-40C to +100C ambient) |
| Mounting Type | Surface Mount (Flip-Chip BGA) | Surface Mount (FC-FBGA) |
| Process Node | 20 nm | — |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Embedded Memory | M20K blocks | — |
| Transceivers | [DATA_NEEDED: transceiver count and data rate] | — |
| Hard Memory Controllers | DDR4 with hard PHY | — |
| PCIe Hard IP | PCI Express Gen3 | — |
| RoHS Status | Compliant | Compliant |
| Lead-Free | Yes | — |
| MSL Level | [DATA_NEEDED: MSL rating] | — |
| Family | — | Arria 10 SX SoC FPGA |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 1.5 GHz |
| Process Technology | — | 20 nm TSMC |
| Package Code | — | F35 / 1152-BGA |
| Ball Pitch | — | 1.0 mm |
| Supply Voltage (Core) | — | 0.9 V |
| Connectivity | — | SPI, UART/USART, EBI/EMI, USB, GbE, PCIe |
| Memory Interface | — | DDR3, DDR4, LPDDR3 (via HPS/FPGA controllers) |