10AS057K2F35I1HG - Arria 10 SX SoC FPGA, 570K LE, 1152-FCBGA | Intel
MPN: 10AS057K2F35I1HG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4682.11 | $4,682.11 |
| 10 | $4450 | $44,500.00 |
| 50 | $4220 | $211,000.00 |
| 100 | $4015 | $401,500.00 |
| 250 | $3820 | $955,000.00 |
Drop-in alternatives for 10AS057K2F35I1HG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS057K2F35E1HG
✅ Drop-In✓ In Stock
$1995 / Unit
View Datasheet →10AS057K2F35E2SG
✅ Drop-In✓ In Stock
$2304.55 / Unit
View Datasheet →10AS057K2F35E2LG
✅ Drop-In✓ In Stock
$3450 / Unit
View Datasheet →10AS066K2F35I1HG
✅ Drop-In📋 Reference alternative (not in catalog)
10AS057K1F35I1HG
✅ Drop-In✓ In Stock
$5210 / Unit
View Datasheet →10AS057K2F35I1HG Maximum Ratings & Electrical Characteristics
| Device Family | Arria 10 SX SoC FPGA |
| Logic Elements | 570K |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Fabric Frequency | 1.5 GHz |
| User I/O Count | 396 |
| Package | 1152-FBGA, FC (35x35 mm) |
| Speed Grade | K2 (mid) |
| Temperature Grade | Industrial (I1: -40C to +100C) |
| Mounting Type | Surface Mount (Flip-Chip BGA) |
| Process Node | 20 nm |
| Embedded Memory | M20K blocks |
| Hard Memory Controllers | DDR4 with hard PHY |
| PCIe Hard IP | PCI Express Gen3 |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AS057K2F35I1HG 1152-fbga, fc (35x35 mm) Pin Configuration Guide
Complete pinout information for 10AS057K2F35I1HG (1152-fbga, fc (35x35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS057K2F35I1HG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS057K2F35I1HG is suitable for 6 applications: Wireless Baseband Processing, Radar and Electronic Warfare Signal Chains, Industrial Machine Vision, Broadcast Video Processing, High-Performance Embedded Compute, Medical Imaging Equipment.
Wireless Baseband Processing
The 10AS057K2F35I1HG's 570K logic elements and embedded variable-precision DSP blocks deliver the throughput needed for multi-antenna wireless baseband signal chains, including LTE/5G NR channel decoding, crest-factor reduction (CFR), and digital predistortion (DPD). The dual-core ARM Cortex-A9 MPCore runs the Layer-2/3 stack, MAC scheduler, and Ethernet backhaul, while the FPGA fabric handles the deterministic, sample-rate DSP. With 396 user I/O plus integrated multi-gigabit transceivers and hard PCI Express Gen3, the device interfaces to RFICs, ADCs/DACs, and host processors without external glue logic. Power estimation: 20-35 W typical at full LTE 4x4 MIMO utilization. This makes it an ideal SoC FPGA for small-cell and macro base station designs.
Recommended
Radar and Electronic Warfare Signal Chains
The 10AS057K2F35I1HG suits phased-array radar and EW receivers that demand deterministic latency and high compute density. The 570K LE fabric plus hardened DSP blocks execute FFTs, pulse compression, and beamforming at sample rates beyond CPU capability, while the ARM Cortex-A9 HPS hosts the control plane, threat library, and Ethernet/serial recorder interfaces. Hardened DDR4 with PHY simplifies the high-bandwidth capture/playback buffer, and PCI Express Gen3 supports direct attach to FPGAs or CPUs for back-end processing. Industrial (I1) -40C to +100C temperature operation covers outdoor and shipborne enclosures. Estimated throughput: tens of GFLOPS sustained DSP, multiple GSPS ADC interface via LVDS/SerDes.
Recommended
Industrial Machine Vision
The 10AS057K2F35I1HG accelerates high-speed line-scan and area-scan machine vision pipelines, executing pre-processing (flat-field correction, Bayer demosaic, color conversion), feature extraction, and AI inference offload in the FPGA fabric. The dual-core ARM Cortex-A9 HPS runs the vision OS, GigE Vision / CoaXPress / Camera Link stacks, and PROFINET/EtherCAT industrial networking. Industrial (I1) temperature grade and 396 user I/O support factory-floor deployment with multiple cameras and discrete I/O. Power: 15-25 W typical for 4-camera systems. Compared with a CPU-only vision system, this SoC FPGA delivers 5-10x throughput per watt at deterministic frame rates.
Recommended
Broadcast Video Processing
The 10AS057K2F35I1HG handles 4K/UHD broadcast video processing, including real-time HEVC/H.264 encode/decode assist, color space conversion, deinterlacing, scaling, and overlay composition in the 570K LE fabric. The ARM Cortex-A9 HPS runs the broadcaster control plane, transport stream muxing, and IP network interfaces. The 396 user I/O plus high-speed transceivers handle SDI (SMPTE 2022, 424, 2082) interfaces via external PHY or transceiver tiles, and hard PCI Express Gen3 supports ingest from SSD arrays or accelerator cards. Industrial temperature grade supports studio and outside-broadcast use.
Recommended
High-Performance Embedded Compute
The 10AS057K2F35I1HG combines deterministic FPGA acceleration with a Cortex-A9 Linux-capable subsystem, making it ideal for industrial embedded compute nodes that must process high-rate sensor data while also running networking and control-plane software. The hard ARM subsystem runs Yocto or Buildroot Linux with industrial protocols (OPC-UA, MQTT, Modbus/TCP), while the 570K LE fabric accelerates custom DSP, control loops, and cryptography. The 1152-FCBGA 35x35 mm package is a compact form factor for DIN-rail or panel-mount embedded systems. Estimated power budget: 18-30 W at moderate fabric utilization.
Recommended
Medical Imaging Equipment
The 10AS057K2F35I1HG serves as the central compute and accelerator in ultrasound, endoscopy, and CT/MRI front-end systems. The FPGA fabric performs beamforming, FIR filtering, image reconstruction, and real-time display processing, while the ARM Cortex-A9 HPS runs the user interface, network stack, and DICOM storage. The industrial temperature range and high pin count accommodate multi-channel analog front ends and display interfaces. Hardened DDR4 and PCI Express Gen3 simplify high-bandwidth data movement, reducing BOM cost versus a CPU+discrete-FPGA architecture.
Recommended
Recommended Products Summary
Engineering reference data for 10AS057K2F35I1HG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS057K2F35E1HG | 10AS057K2F35E2SG | 10AS057K2F35E2LG | 10AS066K2F35I1HG | 10AS057K1F35I1HG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FBGA, FC (35x35 mm) | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same | 1152-FBGA, FC (35x35 mm) - same |
| Logic Elements | 570K | 570K | 570K | 570K | 660K | 570K |
| Speed Grade | K2 (mid) | K2 (mid) | K2 (mid) | K2 (mid) | K2 (mid) | K1 (slower) |
| Temperature Grade | I1 (industrial, -40C to +100C) | E1 (commercial, 0C to +100C) | E2 (commercial) | E2 (commercial) | I1 (industrial) | I1 (industrial) |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight | Dual ARM Cortex-A9 MPCore + CoreSight |
| User I/O | 396 | 396 | 396 | 396 | [DATA_NEEDED] | 396 |
| Approx. Unit Price (qty 1) | $4,682.11 | Similar (commercial temp, lower) | Similar | Similar | Higher (density upgrade ~10-20%) | Similar |
Key Differentiators
- Industrial temperature grade in the same F35 footprint (vs 10AS057K2F35E1HG)
- 570K LE in the mid-density F35 package (vs 10AS066K2F35I1HG)
- K2 mid speed grade is faster than K1 at same density (vs 10AS057K1F35I1HG)
Design Notes
Estimated: the Arria 10 SX 570K device can dissipate 20-40 W under typical wireless baseband or radar workloads. The 1152-FCBGA 35x35 mm package must be paired with a thermal interface material (TIM) and finned heatsink plus forced-air flow of at least 200 LFM. Use the Intel Arria 10 PowerPlay early power estimator before PCB layout to size cooling and verify junction temperature stays below 100C for industrial (I1) grade. Never rely on the package alone to dissipate power at high toggle rates.
Plan the HPS boot flash, the HPS-to-FPGA bridge clocking, and the HPS EMIF (DDR4) pin assignment in the early schematic stage; mis-assigned HPS EMIF pins cannot be migrated to general-purpose I/O. Use the Intel Arria 10 SoC FPGA pin connection guidelines to route JTAG, configuration, and reference clocks separately from high-speed transceiver channels. Provide a minimum of 4 PCB layers with continuous ground planes under the BGA for transceiver return-path integrity.
Do not assume the HPS can boot from any flash device - the Arria 10 SX HPS only supports specific QSPI/NAND/NOR boot modes and pin assignments per the SoC boot guide. Also, the ARM subsystem contributes a fixed ~5-10 W power floor regardless of fabric utilization, so total-board thermal budgets must include this. Finally, configuration via JTAG requires the 10-pin or 20-pin Altera/Intel header, while passive serial configuration requires an external EPCQ or compatible flash.
Compliance Information
RoHS and REACH compliance per Intel/Altera product page. AEC-Q100 not applicable (FPGA SoC is not an automotive-qualified IC at this density; automotive variants would carry a different ordering code).
