10AS057K2F35I2LG - Arria 10 SX SoC FPGA 570K LE | Intel
MPN: 10AS057K2F35I2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1780 | $17,800.00 |
| 100 | $1695 | $169,500.00 |
| 500 | $1610 | $805,000.00 |
| 1,000 | $1545 | $1,545,000.00 |
Drop-in alternatives for 10AS057K2F35I2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS057K2F35I1HG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →10AS057K2F35E2LG
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View Datasheet →10AS057K2F35E2SG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →10AS057K1F35I1HG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →10AS048K4F35I3LG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →10AS048K4F35E3LG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →10AS057K2F35I2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 1.5 GHz |
| Process Technology | 20 nm TSMC |
| Package | 1152-pin FC-FBGA (F35), 35 x 35 mm |
| Package Code | F35 / 1152-BGA |
| Ball Pitch | 1.0 mm |
| Temperature Grade | Industrial (-40C to +100C ambient) |
| Speed Grade | -I2 |
| Supply Voltage (Core) | 0.9 V |
| Connectivity | SPI, UART/USART, EBI/EMI, USB, GbE, PCIe |
| Memory Interface | DDR3, DDR4, LPDDR3 (via HPS/FPGA controllers) |
| Mounting Type | Surface Mount (FC-FBGA) |
| RoHS Status | Compliant |
10AS057K2F35I2LG f35 / 1152-bga Pin Configuration Guide
Complete pinout information for 10AS057K2F35I2LG (f35 / 1152-bga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS057K2F35I2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS057K2F35I2LG is suitable for 6 applications: Wireless Baseband Processing, Military Radar and Electronic Warfare, Broadcast Video Encoding and Processing, Industrial Machine Vision, Medical Imaging Equipment, High-Performance Embedded Computing (HPEC).
Wireless Baseband Processing
The 10AS057K2F35I2LG's 570K logic elements and integrated dual ARM Cortex-A9 HPS make it well-suited for 4G/5G small-cell baseband processing. Its 20nm process delivers the DSP throughput required for LTE PHY-layer acceleration while the 1.5 GHz HPS runs the MAC scheduler and OAM stack. The industrial temperature grade supports outdoor small-cell deployments. Multiple high-speed transceiver channels interface directly to RF front-end converters via JESD204B/C, replacing discrete FPGA+CPU designs with a single SoC.
Recommended
Military Radar and Electronic Warfare
Arria 10 SX devices are QML-class candidates in defense applications, and the 10AS057K2F35I2LG's combination of 570K LEs and industrial temperature grade supports phased-array radar beamforming and EW receiver processing. The HPS handles threat-library lookups and operator interfaces, while the FPGA fabric runs pulse-Doppler FFTs and direction-finding algorithms. Its transceiver density supports multi-channel digital receiver arrays without external ADC/FGPA bridges.
Recommended
Broadcast Video Encoding and Processing
The 570K logic elements plus hard ARM Cortex-A9 HPS enable real-time HEVC/H.265 broadcast encoder designs at 4K60 resolution. The FPGA fabric accelerates motion estimation, deblocking, and SAO filters, while the HPS manages IP transport streams (SRT, RTMP, MPEG-TS) and HTTP server interfaces. The 1152-BGA F35 package's high pin count supports multiple 12G-SDI input/output channels and HDMI 2.0 bridging.
Recommended
Industrial Machine Vision
The 10AS057K2F35I2LG's Coherent Accelerator Processor (ACP) bridge allows low-latency FPGA-to-CPU image sharing for line-scan and area-scan machine vision. The dual-core ARM runs the vision pipeline orchestrator and GigE Vision / Camera Link host stack, while the FPGA fabric implements Bayer demosaic, lens correction, and CNN-based defect classification. Industrial -40C to +100C operation supports factory-floor deployment without climate control.
Recommended
Medical Imaging Equipment
Mid-range SoC FPGAs like the 10AS057K2F35I2LG power ultrasound beamformers, CT image reconstruction, and endoscopy video processors. The dual-core ARM Cortex-A9 at 1.5 GHz runs the patient-interface touchscreen and DICOM network stack, while the FPGA fabric performs 2D/3D image reconstruction in real time. The industrial temperature range suits portable bedside ultrasound carts, and the 0.9V core rail simplifies IEC 60601-1 patient-leakage isolation design.
Recommended
High-Performance Embedded Computing (HPEC)
Defense and aerospace HPEC systems use Arria 10 SX SoCs to combine sensor I/O, signal processing, and command/control on a single board. The 10AS057K2F35I2LG runs a VPX/OpenVPX SBC profile with 570K LEs for FFT, crypto, and protocol bridge functions, plus the ARM HPS running Linux for situational-awareness GUIs. Its transceiver-rich I/O supports 10 Gigabit Ethernet, Serial RapidIO, and Aurora backplane fabrics.
Recommended
Recommended Products Summary
Engineering reference data for 10AS057K2F35I2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS057K2F35I1HG | 10AS057K2F35E2LG | 10AS057K2F35E2SG | 10AS057K1F35I1HG | 10AS048K4F35I3LG | 10AS048K4F35E3LG |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FC-FBGA (F35) 35x35 mm | 1152-FC-FBGA (F35) 35x35 mm - same | 1152-FC-FBGA (F35) 35x35 mm - same | 1152-FC-FBGA (F35) 35x35 mm - same | 1152-FC-FBGA (F35) 35x35 mm - same | 1152-FC-FBGA (F35) 35x35 mm - same | 1152-FC-FBGA (F35) 35x35 mm - same |
| Logic Elements | 570,000 | 570,000 | 570,000 | 570,000 | 570,000 | 480,000 (-15.8%) | 480,000 (-15.8%) |
| Speed Grade | -I2 (Industrial) | -I1 (Industrial, faster) | -E2 (Extended, faster) | -E2 (Extended, faster) | -I1 (Industrial, faster) | -I3 (Industrial, slower) | -E3 (Extended, fastest) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Extended (0C to +100C) | Extended (0C to +100C) | Industrial | Industrial | Extended |
| HPS Core Frequency | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz |
| Transceiver Tier | K2 (mid transceiver count) | K2 | K2 | K2 | K1 (-15% transceivers) | K4 (highest tier) | K4 (highest tier) |
| Ball Finish | LG (Pb-free) | HG (Pb-free halogen-free) | LG (Pb-free) | SG (Pb-free) | HG (Pb-free halogen-free) | LG (Pb-free) | LG (Pb-free) |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
| Approx. Unit Price (qty 1) | $1,850 | $1,920 (+3.8%) | $1,830 (-1.1%) | $1,830 (-1.1%) | $1,720 (-7.0%) | $1,520 (-17.8%) | $1,560 (-15.7%) |
Key Differentiators
- Faster industrial speed grade (-I1) available in same footprint (vs 10AS057K2F35I1HG)
- Lower-cost reduced-logic alternative in same footprint (vs 10AS048K4F35I3LG)
- Reduced-transceiver variant for cost-sensitive designs (vs 10AS057K1F35I1HG)
Design Notes
Estimated: Arria 10 SX devices in the 10AS057 density typically draw 8-15 W from the 0.9V core rail depending on utilization and clock rates. Use a 4-phase PWM controller such as the Renesas ISL6388 or TI TPS53681 with PMBus to power the VCC core. Sequence VCC (0.9V), VCC_HPS (0.9V), and VCC_IO per Intel power-up guidelines to avoid back-powering through I/O cells.
The 1152-FC-FBGA F35 package has a typical theta_JA of approximately 8 C/W with a properly designed heatsink. Estimate: at 12 W total dissipation, junction-to-ambient rise is roughly 96 C above ambient with a passive heatsink, requiring careful thermal management at industrial 85 C ambient. Use a thermal interface material (TIM) with conductivity >3 W/m-K and follow Intel's FCBGA thermal layout reference for via patterns under the die.
The 1.0 mm ball pitch and 35 x 35 mm BGA footprint require an 8-layer PCB minimum with stacked microvias (laser-drilled) and 1-oz copper inner layers. Matched-length impedance control (100 ohm differential for transceivers, 50 ohm single-ended for GPIO) is mandatory. Use Intel's Arria 10 pin connection guidelines to identify which pins require pull-ups, no-connects, or specific decoupling schemes for configuration.
Do not confuse the 'K2' transceiver tier code with the 'F35' package code when sourcing - K2 refers to mid-density transceiver count, F35 to the package outline. Also ensure the HPS boot source (MSEL pins) matches your firmware boot image - QSPI vs SD vs NAND are selected at MSEL reset, not in software. Using non-industrial-grade Arria 10 parts in outdoor deployments is a frequent qualification failure.
Compliance Information
RoHS compliant per Intel/Altera product page; LG ball finish indicates Pb-free. Halogen-free status not specified in verified web data for this exact variant (the 'HG' suffix variants like 10AS057K2F35I1HG explicitly claim halogen-free). AEC-Q100 not applicable - this is an industrial FPGA/SoC, not an automotive-qualified part.
