10AX090N2F45I2SG vs 10AX090N2F45E1SG Comparison
Detailed side-by-side comparison of 10AX090N2F45I2SG by Intel and 10AX090N2F45E1SG by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | 10AX090N2F45I2SG | 10AX090N2F45E1SG |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3,475.00 | $10,250.00 |
| Product Type | FPGA (Field Programmable Gate Array) | — |
| Family | Arria 10 GX | Arria 10 GX |
| Logic Elements | 900,000 | 900,000 |
| Embedded Memory (Bits) | 59,234,104 | — |
| User I/Os | 768 | — |
| Number of LABs/CLBs | 33750 | — |
| Process Technology | 20 nm | 20 nm |
| Core Voltage | 0.9 V | — |
| Operating Temperature | -40C to +100C (Industrial) | -40C to +100C (industrial, I=1 in OPN suffix indicates industrial) |
| Package | 1932-BBGA, F45 (FCBGA flip-chip) | 1932-ball FC-FBGA (F45) |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Speed Grade | -2 | 2 |
| Configuration Method | JTAG / Serial / Parallel flash | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| GTX/Transceivers | [DATA_NEEDED: transceiver count per device variant] | — |
| RoHS Status | Compliant | Compliant |
| Lead-Free | Yes | Yes |
| MSL Level | [DATA_NEEDED: MSL rating] | — |
| Embedded Memory (bits) | — | 59,234,304 |
| Number of User I/O | — | 768 |
| Transceiver Channels | — | 24 |
| Max Transceiver Data Rate | — | 14.1 Gbps |
| Core Voltage (Vcc) | — | 0.85 V to 0.9 V |
| Number of LABs/ALMs | — | [DATA_NEEDED: LAB/ALM count] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Configuration Interface | — | Passive Serial, Fast Passive Parallel, JTAG |
| Hard Memory Controllers | — | DDR3/DDR4 with ECC |
| PCIe Hard IP | — | PCI Express Gen3 x8 (hard IP) |
| Security Features | — | AES-256, SHA-256, public-key (Design Security) |