10AX115N2F45I1SG vs 10AX115N2F45E2SG Comparison
Detailed side-by-side comparison of 10AX115N2F45I1SG by Altera and 10AX115N2F45E2SG by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
10AX115N2F45I1SG - Arria 10 GX FPGA, 1.15M LE, F45 | Intel / Altera
10AX115N2F45I1SG ✓ Active
Specification Comparison
| Parameter | 10AX115N2F45I1SG | 10AX115N2F45E2SG |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7,150.00 | $3,570.00 |
| Family | Arria 10 GX | — |
| Logic Elements | 1,150,000 | 1,150,000 |
| Embedded Memory Bits | 68,857,856 (68.86 Mbit) | 68,857,856 |
| DSP Blocks | 3,036 (18x19 multipliers) | — |
| User I/O Count | 768 | — |
| Package | 1932-ball FC-FBGA (F45, 45 mm) | 1932-ball FCBGA, 45mm body (F45) |
| Process Technology | 20 nm TSMC | Intel 20nm Tri-Gate (FinFET) |
| Core Voltage | 0.9 V | — |
| Speed Grade | I1 (industrial, slowest) | 2 |
| Temperature Grade | Industrial (-40C to +100C) | — |
| Transceivers | 24 (up to 17.4 Gbps) | — |
| PCIe Hard IP | Gen3 x8 | — |
| Memory Interface | DDR4 up to 2666 Mbps, QDR IV | — |
| Adaptive Logic Modules (ALMs) | 427,200 | — |
| MLAB Memory (bits) | 8,812,800 | — |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| RoHS Status | Compliant | Compliant |
| Series | — | Arria 10 GX |
| Embedded Memory Type | — | M20K SRAM blocks |
| DSP Blocks (18x19 Multipliers) | — | 1,518 |
| Maximum User I/Os | — | 768 |
| Transceiver Count | — | [DATA_NEEDED: transceiver count for -2 speed grade] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| Hard Processor Subsystem | — | Dual-core ARM Cortex-A9 (optional HPS configuration) |
| PCI Express Hard IP | — | Gen3 x8 (hardened) |
| Operating Junction Temperature | — | 0C to +100C (commercial grade) |
| Configuration Memory | — | Internal, supports serial and parallel configuration |