10AX115U2F45E1SG vs 10AX115U3F45E2SG Comparison
Detailed side-by-side comparison of 10AX115U2F45E1SG by Intel and 10AX115U3F45E2SG by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | 10AX115U2F45E1SG | 10AX115U3F45E2SG |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13,900.00 | $5,800.00 |
| Family | Arria 10 GX | Arria 10 GX |
| Logic Elements | 1,150,000 | — |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | — |
| Embedded Memory (bits) | 68,857,600 | — |
| Embedded Memory (Mbits) | 68.86 Mbit | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | Variable-precision, hardened floating-point |
| 18x18 Multipliers | 1,518 | — |
| User I/O Pins | 480 | — |
| Transceiver Channels | 24 | — |
| Max Transceiver Data Rate | 17.4 Gbps (chip-to-chip/backplane) | — |
| Hard Memory Controllers | 6 (DDR4/DDR3/QDRII+/RLDRAM3) | 2 (DDR4/DDR3/QDRII+/RLDRAM3) |
| PCIe Hard IP | PCIe Gen3 x8 | — |
| Process Node | TSMC 20 nm | 20 nm Tri-Gate (Intel) |
| Core Voltage | 0.9 V | — |
| Package | 1932-ball FCBGA, 45 x 45 mm, 1.0 mm pitch | 1932-ball FCBGA (F45, 45×45 mm, 1.0 mm pitch) |
| Grade | E1 (extended industrial, -40C to +100C) | — |
| RoHS Status | Compliant | — |
| Logic Elements (LE) | — | 1,150,000 |
| Adaptive Logic Modules (ALM) | — | 427,200 |
| Embedded Memory Bits | — | 68,857,856 (≈ 52.99 Mbit) |
| Number of Transceivers | — | [DATA_NEEDED: per-die transceiver count, F45 package variant] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| Hard PCIe Gen3 IP Blocks | — | 2 × PCIe Gen3 (x8/x4/x2/x1) |
| Speed Grade | — | -2 (E2 commercial/extended) |
| Operating Temperature | — | Industrial (junction -40 °C to +100 °C) – device grade U |
| Supply Voltage Core | — | [DATA_NEEDED: VCC/VCCP core voltage] |
| Configuration Method | — | FPGA configuration via serial/parallel flash, JTAG |
| RoHS Compliance | — | Compliant |
| MSL Level | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |