5CSEBA2U19C7N vs 5CSEBA2U19C6N Comparison

Detailed side-by-side comparison of 5CSEBA2U19C7N by Intel and 5CSEBA2U19C6N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter 5CSEBA2U19C7N 5CSEBA2U19C6N
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $16.90 $74.60
Family Cyclone V SE SoC FPGA Cyclone V SE SoC FPGA
Logic Elements 25,000 LE 25 K
Adaptive Logic Modules (ALMs) 9,430 ALM —
ALUTs 9,430 —
DSP Blocks 66 (variable-precision 18x18) Variable-precision DSP
Embedded Memory 1,400 Kbits (M9K + MLAB) —
HPS Processor Dual ARM Cortex-A9 MPCore with CoreSight —
HPS Maximum Clock Frequency 925 MHz 925 MHz
L1 Cache (per core) 32 KB I-cache + 32 KB D-cache —
L2 Cache 512 KB shared 512 KB shared
User I/O Pins [DATA_NEEDED: exact user I/O count] —
Package 484-pin UBGA (19x19 mm, 1.0 mm pitch) 484-pin UBGA (19x19 mm)
Speed Grade C7 —
Operating Temperature Commercial / Industrial (TJ from data) —
Process Technology TSMC 28 nm low-power TSMC 28 nm low-power
Mounting Type Surface Mount (BGA) Surface Mount
MSL Level [DATA_NEEDED: MSL rating] —
RoHS Status Compliant Compliant
Hard Processor System — Dual ARM Cortex-A9 MPCore with CoreSight
Operating Temperature Grade — Commercial (other)
Memory Interfaces — DDR2, DDR3, LPDDR2 with ECC
HPS Peripherals — GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC
L1 Cache per Core — 32 KB I-cache + 32 KB D-cache
FPGA-to-HPS Bridges — AXI-32/AXI-64, FPGA-to-SDRAM ports

Datasheets & Resources

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