5CSEBA5U19C6N vs 5CSEBA5U19C7N Comparison
Detailed side-by-side comparison of 5CSEBA5U19C6N by Intel and 5CSEBA5U19C7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
5CSEBA5U19C6N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19C6N ✓ ActiveSpecification Comparison
| Parameter | 5CSEBA5U19C6N | 5CSEBA5U19C7N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $118.20 | $99.20 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 85K | 85,000 |
| Hard Processor Cores | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum HPS Clock Frequency | 925 MHz | — |
| Package | 484-UBGA (19x19 mm) | 484-UBGA (UBGAmobile, 19x19 mm) |
| Process Technology | 28 nm low-power | — |
| Embedded Memory | Approximately 4,450 Kbits (per family datasheet) | M10K + MLAB blocks, ~4,450 Kbits total |
| DSP Blocks | 87 variable-precision | Variable-precision, 18x18 / 27x27 multipliers |
| PLLs | 8 fractional | — |
| Maximum User I/O | 364 (per family datasheet) | — |
| Peripherals | CAN, USB OTG, Gigabit Ethernet, DDR3 controller, PCIe Gen2, I2C, SPI, UART | — |
| Operating Temperature | Commercial (0C to +85C) per C6 speed/temp code | 0C to +85C (commercial, junction) |
| Speed Grade | C6 | -7 (standard) |
| RoHS Status | Compliant (per Altera product page) | — |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz per core |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| MSL Level | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |