5CSEBA5U19C6N vs 5CSEBA5U19C7N Vergleich
Detaillierter Direktvergleich von 5CSEBA5U19C6N von Intel und 5CSEBA5U19C7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
5CSEBA5U19C6N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19C6N ✓ AktivSpezifikationsvergleich
| Parameter | 5CSEBA5U19C6N | 5CSEBA5U19C7N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $118,20 | $99,20 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 85K | 85,000 |
| Hard Processor Cores | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum HPS Clock Frequency | 925 MHz | — |
| Gehäuse | 484-UBGA (19x19 mm) | 484-UBGA (UBGAmobile, 19x19 mm) |
| Process Technology | 28 nm low-power | — |
| Embedded Memory | Approximately 4,450 Kbits (per family datasheet) | M10K + MLAB blocks, ~4,450 Kbits total |
| DSP Blocks | 87 variable-precision | Variable-precision, 18x18 / 27x27 multipliers |
| PLLs | 8 fractional | — |
| Maximum User I/O | 364 (per family datasheet) | — |
| Peripherals | CAN, USB OTG, Gigabit Ethernet, DDR3 controller, PCIe Gen2, I2C, SPI, UART | — |
| Betriebstemperatur | Commercial (0C to +85C) per C6 speed/temp code | 0C to +85C (commercial, junction) |
| Speed Grade | C6 | -7 (standard) |
| RoHS-Status | Compliant (per Altera product page) | — |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz per core |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| MSL-Level | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |