5CSEBA5U19C8N vs 5CSEBA5U23C8N Comparison
Detailed side-by-side comparison of 5CSEBA5U19C8N by Intel and 5CSEBA5U23C8N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
5CSEBA5U19C8N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19C8N ✓ ActiveAltera
5CSEBA5U23C8N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Altera
5CSEBA5U23C8N ✓ ActiveSpecification Comparison
| Parameter | 5CSEBA5U19C8N | 5CSEBA5U23C8N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $88.75 |
| Family | Cyclone V SE (SoC FPGA) | Cyclone V SE SoC FPGA |
| Logic Elements | 85,000 LE | 85,000 |
| Adaptive Logic Modules (ALMs) | 32,070 ALM | — |
| Embedded Memory | 3.88 Mbit | Approx. 3.97 Mbits |
| Processor Cores | Dual ARM Cortex-A9 MPCore | — |
| Core Maximum Frequency | 925 MHz (datasheet); 600 MHz commercial speed grade | — |
| L1 Cache (Instruction) | 2 x 32 kB | — |
| L1 Cache (Data) | 2 x 32 kB | — |
| L2 Cache | 512 kB shared | — |
| FPGA User I/Os | 66 I/O | — |
| Process Technology | 28 nm TSMC | — |
| Core Voltage | 1.1 V | — |
| Mounting Type | Surface Mount (SMD/SMT) | Surface Mount (BGA) |
| Package | 484-UBGA (U19, 19x19 mm) | 672-pin UBG / UFBGA, 23 x 23 mm |
| Ball Pitch | [DATA_NEEDED: ball pitch in mm] | — |
| Operating Temperature | 0C to +85C (commercial) | 0 °C to +85 °C (commercial 'C' grade) |
| Speed Grade | C8 (0.85 ns, commercial) | 8 |
| RoHS Status | Compliant | Compliant |
| HPS Cores | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 600 MHz |
| DSP Blocks | — | 87 variable-precision DSP blocks |
| Maximum User I/O | — | 145 |
| Transceivers | — | 3.125 Gbps (SE variant) |
| Process Node | — | 28 nm TSMC low-power |
| Core Voltage (VCC) | — | 1.1 V |
| Memory Interface | — | DDR3 / DDR3L / LPDDR2 (HPS + FPGA) |