5CSEBA5U19I7N vs 5CSEBA6U19I7N Comparison
Detailed side-by-side comparison of 5CSEBA5U19I7N by Intel and 5CSEBA6U19I7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
5CSEBA5U19I7N - Cyclone V SE SoC FPGA 85K LE Dual ARM Cortex-A9 | Intel
5CSEBA5U19I7N ✓ ActiveIntel
5CSEBA6U19I7N - Cyclone V SE SoC FPGA, 110K LE, Dual ARM Cortex-A9 800MHz | Intel
5CSEBA6U19I7N ✓ ActiveSpecification Comparison
| Parameter | 5CSEBA5U19I7N | 5CSEBA6U19I7N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $119.85 | $142.75 |
| Product Type | SoC FPGA (System-on-Chip FPGA) | — |
| Series | Cyclone V SE | 5CSEBA6 |
| Logic Elements | 85,000 | 110,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | Dual-core ARM Cortex-A9 MPCore |
| Core Frequency | 800 MHz (typical), up to 925 MHz | — |
| Process Technology | 28 nm TSMC low-power | TSMC 28 nm low-power |
| Package | 484-pin UBG (UFBGA) 19x19 mm | 484-pin UBGAFBGA (UBGA-484, 19x19 mm) |
| Supply Voltage | 1.1 V core | Multi-rail (1.1 V core, 1.5/1.8/2.5/3.0/3.3 V I/O) |
| FPGA User I/O | 66 (per datasheet front-page snippet) | — |
| Embedded Memory | Approximately 4,450 Kbits | 4.45 Mbits (M10K + MLAB) |
| DSP Blocks | 87 variable-precision (18x18 multipliers) | 112 (18x18 multipliers) |
| Transceivers | Up to 5 Gbps (Cyclone V SE feature) | Up to 9 channels, 3.125 Gbps |
| HPS Peripherals | USB 2.0 OTG, EMAC, CAN, SPI, I2C, UART, SD/MMC, NAND | — |
| Operating Temperature | -40C to +100C (Industrial grade, suffix I) | -40C to +100C (Industrial) |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | Compliant (per Heisener listing and product family) | Compliant |
| Family | — | Cyclone V SE SoC FPGA |
| Device Variant | — | 5CSEA6 (U19 package, 110K LE) |
| HPS Maximum Frequency | — | 800 MHz |
| Hard Memory Controller | — | DDR3, DDR3L, LPDDR2 |
| PLLs | — | 6 (FPGA) + 3 (HPS) |
| User I/O Banks | — | 8 |
| Maximum User I/O | — | 288 (package-dependent) |
| Configuration Modes | — | JTAG, Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP) |