5CSEBA6U19C6N vs 5CSEBA2U19C6N Comparison

Detailed side-by-side comparison of 5CSEBA6U19C6N by Altera and 5CSEBA2U19C6N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter 5CSEBA6U19C6N 5CSEBA2U19C6N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $194.15 $74.60
Manufacturer Altera (Intel) —
Series Cyclone V SE SoC FPGA —
Device Variant 5CSEA6 (U19 package) —
Logic Elements 110K 25 K
HPS Architecture Dual ARM Cortex-A9 MPCore with CoreSight —
HPS Frequency 925 MHz —
FPGA Speed Grade -6 (industrial) —
Package 484-UBGA (UBGА, 19x19 mm) 484-pin UBGA (19x19 mm)
Pin Count 484 —
Process Technology TSMC 28 nm low-power TSMC 28 nm low-power
User I/O 66 (per Heisener) / configurable LVDS/LVCMOS —
Hard IP Blocks PCIe Gen2, multi-port memory controller, ARM Cortex-A9 HPS —
DSP Blocks Variable-precision DSP Variable-precision DSP
Memory Embedded M10K blocks —
Operating Temperature -40C to +100C (industrial) —
Mounting Type Surface Mount (BGA) Surface Mount
RoHS Status Compliant (per Altera/Intel product page) Compliant
MSL Level 3 (per BGA package) —
Family — Cyclone V SE SoC FPGA
Hard Processor System — Dual ARM Cortex-A9 MPCore with CoreSight
HPS Maximum Clock Frequency — 925 MHz
Operating Temperature Grade — Commercial (other)
Memory Interfaces — DDR2, DDR3, LPDDR2 with ECC
HPS Peripherals — GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC
L2 Cache — 512 KB shared
L1 Cache per Core — 32 KB I-cache + 32 KB D-cache
FPGA-to-HPS Bridges — AXI-32/AXI-64, FPGA-to-SDRAM ports

Datasheets & Resources

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