A3PE3000L-1FG896I vs A3PE3000L-FGG896M Comparison
Detailed side-by-side comparison of A3PE3000L-1FG896I by Microchip Technology and A3PE3000L-FGG896M by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
A3PE3000L-1FG896I - 3M-Gate Low-Power Flash FPGA | Microchip
A3PE3000L-1FG896I ✓ ActiveMicrochip Technology
A3PE3000L-FGG896M - 3M-Gate Low-Power Flash FPGA | Microchip
A3PE3000L-FGG896M ✓ ActiveSpecification Comparison
| Parameter | A3PE3000L-1FG896I | A3PE3000L-FGG896M |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Family | ProASIC3L (Flash FPGA) | ProASIC3L (Flash-based FPGA) |
| System Gates | 3,000,000 | 3,000,000 |
| Logic Cells | 75,264 | 75,264 |
| User I/O | 620 | — |
| Core Voltage | 1.2 V to 1.5 V | 1.2 V to 1.5 V |
| Process Technology | 130 nm CMOS flash | 130-nm, 7-layer metal (6 copper), flash-based CMOS |
| Maximum Frequency | 892.86 MHz | — |
| Package | 896-ball FBGA (FG896), 1.00 mm pitch | 896-ball FBGA (FGG896), 1 mm pitch |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40C to +85C (Industrial) | 0 to 70 C |
| Configuration Memory | On-chip Flash (non-volatile, single chip) | — |
| Low Power Feature | Flash*Freeze Technology | — |
| JTAG Boundary Scan | IEEE 1149.1 | — |
| Input Options | Schmitt trigger option on single-ended inputs | — |
| Pull Options | Weak pull-up / pull-down | — |
| Reprogrammability | Live reprogrammable | — |
| Speed Grade | -1 | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| User I/Os | — | Up to 616 (620 per DigiKey listing) |
| Embedded SRAM | — | 504 kbits true dual-port |
| Supply Voltage | — | 1.5 V |
| Logic Family | — | CMOS |
| Configuration | — | Non-volatile flash, live-at-power-up Level 0, single-chip |
| Low-Power Feature | — | Flash*Freeze technology |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| Input Features | — | Schmitt trigger option on single-ended inputs; weak pull-up/pull-down |