A3PE3000L-1PQ208 vs A3PE3000L-PQ208 Comparison
Detailed side-by-side comparison of A3PE3000L-1PQ208 by Microchip Technology and A3PE3000L-PQ208 by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
A3PE3000L-1PQ208 - ProASIC3L Flash FPGA 208-PQFP | Microchip
A3PE3000L-1PQ208 ✓ ActiveMicrochip Technology
A3PE3000L-PQ208 - 3M Gate Low-Power Flash FPGA | Microchip
A3PE3000L-PQ208 ✓ ActiveSpecification Comparison
| Parameter | A3PE3000L-1PQ208 | A3PE3000L-PQ208 |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $310.69 |
| Family | ProASIC3L (Low Power Flash FPGA) | ProASIC3L (ProASIC3EL) |
| System Gates | 3M gates | 3,000,000 |
| Logic Elements | 35K LEs | — |
| User I/O | 147 | — |
| Core Voltage | 1.2 V | 1.2 V |
| Core Voltage Range | 1.2 V to 1.5 V | — |
| Process Technology | 130 nm flash | 130 nm, 7-layer metal (6 copper) CMOS |
| Characteristic Frequency | 892.86 MHz | — |
| Configuration Memory | On-chip nonvolatile flash (Instant On) | — |
| Low Power Feature | Flash*Freeze technology | — |
| Package | 208-BFQFP (PQFP-208) | 208-BFQFP (PQ208), 1.0 mm pitch |
| Mounting Type | Surface Mount | Surface Mount |
| Packaging | Tray | Tray |
| MSL Level | 3 (168 hours) | — |
| ECCN | 3A001A7A | — |
| HTSUS | 8542.39.0001 | — |
| RoHS Status | [DATA_NEEDED: RoHS status for A3PE3000L-1PQ208] | RoHS Non-Compliant (contains lead) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C |
| Embedded SRAM | — | 504 kbits true dual-port |
| User I/Os (PQ208) | — | 147 |
| Supply Voltage | — | 1.5 V |
| Maximum Frequency | — | 781.25 MHz |
| Logic Family | — | CMOS |
| Program Type | — | Flash-based, In-System Programmable |
| Power-Up Behavior | — | Live At Power-Up Level 0 |
| Configuration | — | Single-chip solution (no external boot device) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |