ADC1412D080HN-C18 vs ADC1412D080HN-C1 Comparison

Detailed side-by-side comparison of ADC1412D080HN-C18 by Renesas Electronics and ADC1412D080HN-C1 by Renesas Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Renesas Electronics
ADC1412D080HN-C18 ADC1412D080HN-C18 - Dual 14-bit 80MSPS ADC, LVDS DDR | Renesas

ADC1412D080HN-C18 - Dual 14-bit 80MSPS ADC, LVDS DDR | Renesas

ADC1412D080HN-C18 Obsolete
Renesas Electronics
ADC1412D080HN-C1 ADC1412D080HN-C1 - Dual 14-bit 80MSPS ADC | Renesas

ADC1412D080HN-C1 - Dual 14-bit 80MSPS ADC | Renesas

ADC1412D080HN-C1 Obsolete

Specification Comparison

Parameter ADC1412D080HN-C18 ADC1412D080HN-C1
Brand Renesas Electronics Renesas Electronics
Category ADC/DAC ADC/DAC
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $18.25 $31.90
Resolution 14 bit 14 bits
Number of Channels 2 —
Sample Rate (per channel) 80 Msps —
Architecture Pipelined Pipelined
Output Interface CMOS or LVDS DDR (selectable) —
Input Channels 2 (differential or single-ended) —
Package 64-VFQFPN (HVQFN) 9x9 mm with exposed pad 64-VFQFPN / HVQFN-64 (9x9 mm, 0.85 mm height, SOT804-6)
Mounting Type Surface Mount Surface Mount
Pin Count 64 64
Family Sample Rate Options 65 / 80 / 105 / 125 Msps —
Family Series ADC1412D SER —
Operating Temperature [DATA_NEEDED: operating temperature range] -40C to +85C (industrial grade)
Supply Voltage [DATA_NEEDED: supply voltage] —
Power Consumption [DATA_NEEDED: power consumption per channel] —
SNR [DATA_NEEDED: signal-to-noise ratio] —
SFDR [DATA_NEEDED: spurious-free dynamic range] —
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
MSL Level [DATA_NEEDED: moisture sensitivity level] [DATA_NEEDED: Moisture Sensitivity Level]
Number of Input Channels — 2 (dual, simultaneous sampling)
Sampling Rate — 80 MSPS
Input Type — Differential analog inputs
Digital Output Interface — CMOS or LVDS DDR (selectable)
Configuration Interface — 3-wire SPI-compatible serial
Input Clock — Sample-rate dependent, single-ended or differential clock input
Supply Voltage (AVDD) — 3.3 V (per package datasheet family)
Screening Level — Industrial
Lead-Free Finish — [DATA_NEEDED: lead-free / matte tin / NiPdAu]

Datasheets & Resources

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