ADC1412D080HN-C18 vs ADC1412D080HN-C1 Comparaison

Comparaison détaillée côte à côte de ADC1412D080HN-C18 par Renesas Electronics et ADC1412D080HN-C1 par Renesas Electronics. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.

Renesas Electronics
ADC1412D080HN-C18 ADC1412D080HN-C18 - Dual 14-bit 80MSPS ADC, LVDS DDR | Renesas

ADC1412D080HN-C18 - Dual 14-bit 80MSPS ADC, LVDS DDR | Renesas

ADC1412D080HN-C18 Obsolete
Renesas Electronics
ADC1412D080HN-C1 ADC1412D080HN-C1 - Dual 14-bit 80MSPS ADC | Renesas

ADC1412D080HN-C1 - Dual 14-bit 80MSPS ADC | Renesas

ADC1412D080HN-C1 Obsolete

Comparaison des spécifications

Paramètre ADC1412D080HN-C18 ADC1412D080HN-C1
Marque Renesas Electronics Renesas Electronics
Catégorie ADC/DAC ADC/DAC
Statut du cycle de vie Obsolete Obsolete
Statut du stock In Stock In Stock
Prix unitaire (USD) $18,25 $31,90
Résolution 14 bit 14 bits
Number of Channels 2 —
Sample Rate (per channel) 80 Msps —
Architecture Pipelined Pipelined
Output Interface CMOS or LVDS DDR (selectable) —
Input Channels 2 (differential or single-ended) —
Boîtier 64-VFQFPN (HVQFN) 9x9 mm with exposed pad 64-VFQFPN / HVQFN-64 (9x9 mm, 0.85 mm height, SOT804-6)
Type de montage Surface Mount Surface Mount
Nombre de broches 64 64
Family Sample Rate Options 65 / 80 / 105 / 125 Msps —
Family Series ADC1412D SER —
Température de fonctionnement [DATA_NEEDED: operating temperature range] -40C to +85C (industrial grade)
Tension d'alimentation [DATA_NEEDED: supply voltage] —
Power Consumption [DATA_NEEDED: power consumption per channel] —
SNR [DATA_NEEDED: signal-to-noise ratio] —
SFDR [DATA_NEEDED: spurious-free dynamic range] —
Statut RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Niveau MSL [DATA_NEEDED: moisture sensitivity level] [DATA_NEEDED: Moisture Sensitivity Level]
Number of Input Channels — 2 (dual, simultaneous sampling)
Fréquence d'échantillonnage — 80 MSPS
Input Type — Differential analog inputs
Digital Output Interface — CMOS or LVDS DDR (selectable)
Configuration Interface — 3-wire SPI-compatible serial
Input Clock — Sample-rate dependent, single-ended or differential clock input
Supply Voltage (AVDD) — 3.3 V (per package datasheet family)
Screening Level — Industrial
Lead-Free Finish — [DATA_NEEDED: lead-free / matte tin / NiPdAu]

Fiches techniques et ressources

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