ADC1412D080HN-C18 vs ADC1412D080HN-C1 Vergleich
Detaillierter Direktvergleich von ADC1412D080HN-C18 von Renesas Electronics und ADC1412D080HN-C1 von Renesas Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Renesas Electronics
ADC1412D080HN-C18 - Dual 14-bit 80MSPS ADC, LVDS DDR | Renesas
ADC1412D080HN-C18 ObsoleteSpezifikationsvergleich
| Parameter | ADC1412D080HN-C18 | ADC1412D080HN-C1 |
|---|---|---|
| Marke | Renesas Electronics | Renesas Electronics |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,25 | $31,90 |
| Auflösung | 14 bit | 14 bits |
| Number of Channels | 2 | — |
| Sample Rate (per channel) | 80 Msps | — |
| Architecture | Pipelined | Pipelined |
| Output Interface | CMOS or LVDS DDR (selectable) | — |
| Input Channels | 2 (differential or single-ended) | — |
| Gehäuse | 64-VFQFPN (HVQFN) 9x9 mm with exposed pad | 64-VFQFPN / HVQFN-64 (9x9 mm, 0.85 mm height, SOT804-6) |
| Montageart | Surface Mount | Surface Mount |
| Pin-Anzahl | 64 | 64 |
| Family Sample Rate Options | 65 / 80 / 105 / 125 Msps | — |
| Family Series | ADC1412D SER | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial grade) |
| Versorgungsspannung | [DATA_NEEDED: supply voltage] | — |
| Power Consumption | [DATA_NEEDED: power consumption per channel] | — |
| SNR | [DATA_NEEDED: signal-to-noise ratio] | — |
| SFDR | [DATA_NEEDED: spurious-free dynamic range] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| MSL-Level | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: Moisture Sensitivity Level] |
| Number of Input Channels | — | 2 (dual, simultaneous sampling) |
| Abtastrate | — | 80 MSPS |
| Input Type | — | Differential analog inputs |
| Digital Output Interface | — | CMOS or LVDS DDR (selectable) |
| Configuration Interface | — | 3-wire SPI-compatible serial |
| Input Clock | — | Sample-rate dependent, single-ended or differential clock input |
| Supply Voltage (AVDD) | — | 3.3 V (per package datasheet family) |
| Screening Level | — | Industrial |
| Lead-Free Finish | — | [DATA_NEEDED: lead-free / matte tin / NiPdAu] |