CDK1308AILP40 vs CDK1307DILP40 Comparison

Detailed side-by-side comparison of CDK1308AILP40 by MaxLinear and CDK1307DILP40 by MaxLinear. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter CDK1308AILP40 CDK1307DILP40
Brand MaxLinear MaxLinear
Category ADC/DAC ADC/DAC
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $4.10 $9.60
Resolution 10 bit 13 bit
Maximum Sample Rate 20 MSPS —
Family Sample Rate Options 20 / 40 / 65 / 80 MSPS —
Architecture Proprietary, digital error correction —
Reference Internal (no external reference required) Internal reference circuitry
Digital Interface CMOS, parallel —
Control Interface CMOS —
Power-Down Pin (PD_N) Yes (active low) —
Sleep Pin (SLP_N) Yes (active low) —
Package 40-pin QFN 40-pin QFN
Mounting Type Surface Mount —
Power Consumption Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) —
Operating Temperature Range [DATA_NEEDED: operating temperature range] —
Supply Voltage [DATA_NEEDED: AVDD / DRVDD values] —
RoHS Status Compliant (per distributor listings) —
Manufacturer MaxLinear (formerly Exar Corporation) —
Sampling Rate (max) — 80 MSPS
Power Dissipation (typ) — 60 mW at 80 MSPS
Family Power Grades — 17 / 19 / 33 / 50 / 60 / 75 mW across speed grades
SNR — 72.4 dB at Fin = 8 MHz
Analog Supply Voltage — 1.8 V (core)
I/O Supply Voltage — 1.7 V to 3.6 V
Output Interface — Parallel CMOS
Clock Input — Differential, low-jitter
Track-and-Hold — Highly linear, optimized to Nyquist
Idle Modes — Standby and Power Down
Pin Compatibility — Pin-compatible with CDK1308
Pin Compatibility (family) — Same 40-pin QFN for A/B/C/D speed grades

Datasheets & Resources

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