CDK1308AILP40 vs CDK1307DILP40 对比

详细并排对比 CDK1308AILP40 出自 MaxLinear 和 CDK1307DILP40 出自 MaxLinear。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 CDK1308AILP40 CDK1307DILP40
品牌 MaxLinear MaxLinear
分类 ADC/DAC ADC/DAC
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $4.10 $9.60
分辨率 10 bit 13 bit
Maximum Sample Rate 20 MSPS —
Family Sample Rate Options 20 / 40 / 65 / 80 MSPS —
Architecture Proprietary, digital error correction —
Reference Internal (no external reference required) Internal reference circuitry
Digital Interface CMOS, parallel —
Control Interface CMOS —
Power-Down Pin (PD_N) Yes (active low) —
Sleep Pin (SLP_N) Yes (active low) —
封装 40-pin QFN 40-pin QFN
安装类型 Surface Mount —
Power Consumption Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) —
工作温度范围 [DATA_NEEDED: operating temperature range] —
电源电压 [DATA_NEEDED: AVDD / DRVDD values] —
RoHS 状态 Compliant (per distributor listings) —
Manufacturer MaxLinear (formerly Exar Corporation) —
Sampling Rate (max) — 80 MSPS
Power Dissipation (typ) — 60 mW at 80 MSPS
Family Power Grades — 17 / 19 / 33 / 50 / 60 / 75 mW across speed grades
SNR — 72.4 dB at Fin = 8 MHz
Analog Supply Voltage — 1.8 V (core)
I/O Supply Voltage — 1.7 V to 3.6 V
Output Interface — Parallel CMOS
Clock Input — Differential, low-jitter
Track-and-Hold — Highly linear, optimized to Nyquist
Idle Modes — Standby and Power Down
Pin Compatibility — Pin-compatible with CDK1308
Pin Compatibility (family) — Same 40-pin QFN for A/B/C/D speed grades

数据手册与资源

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