EP1810GM883B vs EP1810JC-45 Comparison
Detailed side-by-side comparison of EP1810GM883B by Altera and EP1810JC-45 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810GM883B | EP1810JC-45 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.40 | $21.10 |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | 48 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 (bidirectional, tri-state) | 48 |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable |
| Operating Temperature | -55 °C to +125 °C (Military, MIL-STD-883B) | — |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | — |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| Mounting Type | Through-hole (PGA socket or PCB through-hole) | Surface Mount |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Equivalent Gates | — | 2100 gates |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Clock Frequency | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Package | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Pin Count | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |
| RoHS Status | — | [DATA_NEEDED: RoHS compliance not stated in verified data] |