EP1810GM883B vs EP1810JC-45 Comparación
Comparación detallada lado a lado de EP1810GM883B por Altera y EP1810JC-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810GM883B | EP1810JC-45 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $125,40 | $21,10 |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | 48 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 (bidirectional, tri-state) | 48 |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable |
| Temperatura de funcionamiento | -55 °C to +125 °C (Military, MIL-STD-883B) | — |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | — |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| Tipo de montaje | Through-hole (PGA socket or PCB through-hole) | Surface Mount |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Equivalent Gates | — | 2100 gates |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Frecuencia de reloj máxima | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Encapsulado | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Recuento de pines | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |
| Estado RoHS | — | [DATA_NEEDED: RoHS compliance not stated in verified data] |