EP1810GM883B vs EP1810JI-35 Comparison
Detailed side-by-side comparison of EP1810GM883B by Altera and EP1810JI-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810GM883B | EP1810JI-35 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.40 | $18.60 |
| Device Family | EP1810 (Classic EPLD) | Classic EPLD |
| Macrocells | 48 | 48 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | 48 |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable | — |
| Operating Temperature | -55 °C to +125 °C (Military, MIL-STD-883B) | -40C to +85C (Industrial) |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | — |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| Mounting Type | Through-hole (PGA socket or PCB through-hole) | Through-Hole (J-lead) |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Package | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Supply Voltage | — | 5 V (typical classic EPLD) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| RoHS Status | — | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| MSL Level | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |