EP1810JC-45 vs EP1810LC-35 Comparison

Detailed side-by-side comparison of EP1810JC-45 by Altera and EP1810LC-35 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Rochester Electronics
EP1810LC-35 EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 ⚠ Last Time Buy

Specification Comparison

Parameter EP1810JC-45 EP1810LC-35
Brand Altera Rochester Electronics
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Last Time Buy
Stock Status In Stock In Stock
Unit Price (USD) $21.10 $49.20
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family EP1810 (Classic EPLD Family) —
Macrocells 48 48
Equivalent Gates 2100 gates 900 usable / 2100 equivalent
Dedicated Inputs 12 —
I/O Pins 48 [DATA_NEEDED: I/O count exact]
Total User I/O 60 —
Propagation Delay (tpd) 45 ns 35 ns (max, '-35' speed grade)
Maximum Clock Frequency 33.3 MHz —
Technology CMOS, UV-erasable CMOS, UV-erasable EPROM
Maximum Supply Voltage 5.25 V —
Package PLCC-68 (QCCJ, J-Lead, windowed ceramic) 68-pin PLCC (J-Lead)
Pin Count 68 —
Package Code QCCJ —
Temperature Grade Commercial —
Mounting Type Surface Mount Surface Mount (socketable)
RoHS Status [DATA_NEEDED: RoHS compliance not stated in verified data] [DATA_NEEDED]
Device Type — EPLD (Erasable Programmable Logic Device)
Series — Classic EP1810
Maximum Operating Frequency — 28.6 MHz
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Operating Temperature — 0C to +70C (commercial)
Configuration Method — UV-erase + EPROM programmer
Programmable Interconnect — Centralized Programmable Interconnect Array (PIA)
Development Tool (legacy) — MAX+PLUS II / A+PLUS
Lead-Free — [DATA_NEEDED]

Datasheets & Resources

Browse All Products Create BOM Request Quote