EP1810JC35 vs EP1810JC-25 Comparison

Detailed side-by-side comparison of EP1810JC35 by Altera and EP1810JC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810JC35 EP1810JC-25
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $6.80
Family Altera Classic EPLD Altera/Intel Classic EPLD (EP1810 series)
Product Type UV-erasable / OTP Complex PLD (EPLD) Classic EPLD (Erasable Programmable Logic Device)
Macrocells 48 48
Logic Gates (typ.) [DATA_NEEDED: logic gates count] —
Maximum User I/O Pins [DATA_NEEDED: user I/O count for PLCC-68] —
Propagation Delay (tPD) 35 ns 25 ns
Maximum Clock Frequency 40 MHz —
Supply Voltage (VCC max) 5.25 V —
Supply Voltage (VCC min) [DATA_NEEDED: VCC minimum] —
Process Technology CMOS EPROM cell —
Operating Temperature 0 C to +70 C (Commercial) -40 °C to 85 °C (industrial, per distributor listings)
Package PLCC-68 (J-lead, ceramic) 28-pin ceramic DIP (J) with quartz window
Package Code QCCJ —
Terminal Form J-BEND —
Number of Terminals 68 —
Programming UV-erase (windowed) or OTP —
Development Tool Altera MAX+plus II / A+plus —
RoHS Status [DATA_NEEDED: RoHS compliance for EP1810JC35] [DATA_NEEDED: RoHS compliance status]
Maximum Toggle Frequency — [DATA_NEEDED: max fMAX]
Input Lines — 60 (including I/O)
I/O Lines — 48
Dedicated Inputs — 12
External Clock Inputs — 4
Supply Voltage (VCC) — 4.75 V to 5.25 V
Technology — CMOS, UV-erasable (windowed ceramic DIP)
Mounting Type — Through-hole
Erasure Method — UV light (windowed package)
Lifecycle Status — NRND (Not Recommended for New Designs)

Datasheets & Resources

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