EP1810JC35 vs EP1810JC-25 对比
详细并排对比 EP1810JC35 出自 Altera 和 EP1810JC-25 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JC35 | EP1810JC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $6.80 |
| Family | Altera Classic EPLD | Altera/Intel Classic EPLD (EP1810 series) |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | 48 |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| 最大时钟频率 | 40 MHz | — |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| 工作温度 | 0 C to +70 C (Commercial) | -40 °C to 85 °C (industrial, per distributor listings) |
| 封装 | PLCC-68 (J-lead, ceramic) | 28-pin ceramic DIP (J) with quartz window |
| Package Code | QCCJ | — |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance for EP1810JC35] | [DATA_NEEDED: RoHS compliance status] |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS, UV-erasable (windowed ceramic DIP) |
| 安装类型 | — | Through-hole |
| Erasure Method | — | UV light (windowed package) |
| 生命周期状态 | — | NRND (Not Recommended for New Designs) |