EP1810JI-35 vs EP1810GC-35 Comparison
Detailed side-by-side comparison of EP1810JI-35 by Intel and EP1810GC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810JI-35 | EP1810GC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.60 | $177.12 |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 16 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | — |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Package | 28-pin JLCC (J-leaded ceramic, windowed) | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Operating Temperature | -40C to +85C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Supply Voltage | 5 V (typical classic EPLD) | [DATA_NEEDED: VCC range] |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Mounting Type | Through-Hole (J-lead) | Through Hole |
| RoHS Status | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | Not applicable (legacy ceramic package) |
| MSL Level | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| Technology | — | CMOS, UV-erasable EPROM cells |
| Number of Pins | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |