EP1810LC-20T vs EP1810LC-25 Comparison

Detailed side-by-side comparison of EP1810LC-20T by Intel and EP1810LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810LC-20T EP1810LC-25
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $8.40
Family Altera Classic EPLD —
Product Type CPLD (Complex Programmable Logic Device) —
Usable Gates 900 gates —
Macrocells 48 48
Logic Array Blocks (LABs) 4 x 12 macrocells —
Maximum Toggle Frequency 50 MHz —
Pin-to-Pin Logic Delay (tPD) 20 ns —
Supply Voltage (VCC) 5 V 5 V (TTL-compatible)
Package Type PLCC-68 (J-lead) —
Mounting Type Surface Mount (socket-compatible) Surface Mount
Configuration Memory On-chip EEPROM (non-volatile) —
Programming Interface JTAG (IEEE 1149.1) and Altera Master/Slave serial —
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: temperature grade for LC package]
Shipping Format Tape & Reel ("T" suffix) —
RoHS Status Non-compliant (legacy 5V PLCC) [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Propagation Delay (tPD) — 25 ns
Dedicated Inputs — 12
I/O Pins — 48
External Clock Inputs — 4
Operating Mode — Turbo-only (no slow-power mode)
Package — 68-pin JLCC (J-leaded ceramic chip carrier)
Package Code — LC = 68-pin JLCC
Technology — CMOS EPLD (erasable programmable logic device)
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Lifecycle Status — Obsolete (legacy Altera Classic family)

Datasheets & Resources

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