EP1810LC-20T - Classic CPLD 900 Gates 48 Macrocells 5V PLCC-68 | Intel
MPN: EP1810LC-20T β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
Drop-in alternatives for EP1810LC-20T β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1810LC-20
β Drop-Inβ In Stock
$7.85 / Unit
View Datasheet βEP1810LC-25
β Drop-Inβ In Stock
$8.4 / Unit
View Datasheet βEP1810LC-15
β Drop-Inπ Reference alternative (not in catalog)
EP1810GM883B
β Drop-Inβ In Stock
$125.4 / Unit
View Datasheet βEP1810GM883
β Drop-Inβ In Stock
$175 / Unit
View Datasheet βEP1810GI-45
β Drop-Inβ In Stock
$56.4 / Unit
View Datasheet βEP1810LC-20T Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 900 gates |
| Macrocells | 48 |
| Logic Array Blocks (LABs) | 4 x 12 macrocells |
| Maximum Toggle Frequency | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | 20 ns |
| Supply Voltage (VCC) | 5 V |
| Package Type | PLCC-68 (J-lead) |
| Mounting Type | Surface Mount (socket-compatible) |
| Configuration Memory | On-chip EEPROM (non-volatile) |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Operating Temperature | 0C to +70C (commercial) |
| Shipping Format | Tape & Reel ("T" suffix) |
| RoHS Status | Non-compliant (legacy 5V PLCC) |
EP1810LC-20T Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 2 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 3 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 4 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 5 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 6 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 7 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 8 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 9 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 10 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 11 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 12 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 13 | GND β Ground |
| Pin 14 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 15 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 16 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 17 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 18 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 19 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 20 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 21 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 22 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 23 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 24 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 25 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 26 | GND β Ground |
| Pin 27 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 28 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 29 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 30 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 31 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 32 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 33 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 34 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 35 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 36 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 37 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 38 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 39 | GND β Ground |
| Pin 40 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 41 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 42 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 43 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 44 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 45 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 46 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 47 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 48 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 49 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 50 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 51 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 52 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 53 | GND β Ground |
| Pin 54 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 55 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 56 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 57 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 58 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 59 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 60 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 61 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 62 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 63 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 64 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 65 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 66 | I/O β User I/O pin (macrocell bidirectional) |
| Pin 67 | VCC β 5V supply voltage |
| Pin 68 | VCC β 5V supply voltage |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810LC-20T is suitable for 6 applications: 5V Bus Address Decoding, Glue Logic Replacement for 74-Series TTL, State Machine Controllers, I/O Expansion and Bus Bridging, Legacy Industrial Control Systems, Prototype and Education Boards.
5V Bus Address Decoding
The EP1810LC-20T is well-suited for 5 V bus address decoding in industrial backplanes and legacy ISA-style systems. Its 48 macrocells provide enough product-term logic to implement multi-chip-select decoders for memory banks and peripherals, while the 5 V VCC interface eliminates the need for level shifters when bridging to 5 V TTL devices. The 20 ns pin-to-pin delay suits system clocks up to 25 MHz. Unlike 3.3 V CPLDs, the EP1810LC-20T directly drives TTL loads without pull-ups, simplifying PCB routing and reducing BOM cost in 5 V-only designs.
Recommended
Glue Logic Replacement for 74-Series TTL
Engineers use the EP1810LC-20T to consolidate dozens of 74LS/74HC glue-logic gates, muxes, and flip-flops into a single non-volatile device, freeing PCB area and reducing assembly cost. The Classic EPLD's product-term architecture maps directly onto standard SSI/MSI TTL functions, allowing straightforward migration from legacy schematics. With 48 macrocells the device can absorb a typical decode-and-control block in a single chip. Its on-chip EEPROM ensures the device powers up in the correct state, eliminating the boot-time race conditions possible with discrete flip-flop implementations.
Recommended
State Machine Controllers
The EP1810LC-20T's registered macrocell output with D-type flip-flops makes it a strong fit for state-machine controllers in industrial controllers, vending machines, and test equipment. Each macrocell can implement one Moore or Mealy state bit, allowing the device to host a 48-state machine with combinatorial next-state logic in a single chip. The 50 MHz toggle frequency supports state-machine clock rates up to 40 MHz after timing margin. Combined with JTAG in-system programming, designers can iterate state tables quickly during development without replacing the device or reworking the PCB.
Recommended
I/O Expansion and Bus Bridging
In I/O expansion and bus-bridging applications, the EP1810LC-20T can serve as a parallel-to-serial converter, bit-banging interface, or low-speed bus arbiter. The 68-pin PLCC provides up to 56 user I/O pins (after power and JTAG pins), sufficient for 16-bit data plus 8-bit address interfaces typical of legacy microcontrollers. The Classic EPLD's deterministic interconnect guarantees fixed propagation delays regardless of logic placement, simplifying worst-case timing analysis. Designers pair it with an MCU or DSP that lacks sufficient I/O, offloading peripheral control logic to the CPLD.
Recommended
Legacy Industrial Control Systems
The EP1810LC-20T remains in service across long-life industrial control systems (PLCs, motor drives, instrumentation) that were designed in the 1990s and require field replacements. Its 5 V PLCC-68 footprint, EEPROM non-volatility, and 20 ns logic delay match the original design exactly. The Classic EPLD's tolerance to electrical noise and industrial-temperature variants (such as the EP1810GI-45) make it suitable for factory-floor environments. For systems with 10+ year field-life support obligations, the EP1810LC-20T is often the only drop-in option without an expensive board redesign.
Recommended
Prototype and Education Boards
The EP1810LC-20T is widely used in university digital-logic laboratories and prototype boards because its PLCC-68 package fits a standard IC socket, allowing students to remove and reprogram the device repeatedly. Programming via JTAG with the legacy Altera ByteBlaster cable and MAX+PLUS II or Quartus software makes it accessible for teaching. The Classic EPLD's transparent architecture shows students direct mapping from logic equations to silicon, unlike modern LUT-based FPGAs that abstract away the underlying structure. Its low I/O count (56 user pins) and modest gate capacity keep introductory design examples tractable.
Recommended
Recommended Products Summary
Engineering reference data for EP1810LC-20T β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810LC-20 | EP1810LC-25 | EP1810LC-15 | EP1810GM883B | EP1810GI-45 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PLCC-68 | PLCC-68 - same | PLCC-68 - same | PLCC-68 - same | PLCC-68 - same | PLCC-68 - same |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 900 |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns | 25 ns (+25%) | 15 ns (-25%) | 20 ns | 45 ns (+125%) |
| Maximum Toggle Frequency | 50 MHz | 50 MHz | 40 MHz (-20%) | 70 MHz (+40%) | 50 MHz | [DATA_NEEDED] |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Military MIL-883B | Industrial (-40C to +85C) |
| Shipping Format | Tape & Reel | Tube | Tube or Tape & Reel | Tube or Tape & Reel | Tube | Tube |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete (military stock only) | Obsolete |
Key Differentiators
- Tape-and-reel shipping format for automated assembly (vs EP1810LC-20)
- Balanced speed grade for 5V industrial designs (vs EP1810LC-25)
- Commercial temperature grade at lower cost (vs EP1810GM883B)
Design Notes
The EP1810LC-20T draws ICC in the range of 50-200 mA from a 5 V supply, with peaks during JTAG programming that can reach 300 mA. Decouple each VCC pin (1, 34, 68) with a 0.1 microfarat X7R ceramic capacitor placed within 5 mm of the pin, and add a single 10 microfarad tantalum or low-ESR electrolytic bulk capacitor at the board entry point. Inadequate decoupling causes voltage droops during EEPROM writes that can corrupt configuration. Place a ferrite bead in series with VCC if the device shares a supply with switching regulators.
The PLCC-68 socket footprint requires a through-hole PLCC socket (AMP 821574-1 or equivalent) for prototype work and field replacement. For production, hand-soldering or reflow of PLCC-68 is feasible but recommended only with a land pattern that includes extended pads. Keep all signal traces at least 3 mm from the socket body to avoid shorts, and route JTAG signals (TMS, TCK, TDI, TDO, nTRST) as a star from the JTAG connector directly to the device pins, with no stubs. Add a 10 kilohm pull-up on nCE (if exposed) to prevent accidental configuration at power-up.
Three common pitfalls when designing with the EP1810LC-20T: (1) leaving unused I/O pins floating creates output-driver contention and excess ICC; configure all unused pins in the MAX+PLUS II / Quartus software as outputs driving ground, or as inputs with internal pull-ups enabled. (2) The device is not hot-pluggable - if a partially inserted socket connects VCC before GND, latch-up can occur; add sequencing circuitry if hot-swap is required. (3) Do not exceed the 5 V absolute-maximum rating on any I/O pin, even briefly during system bring-up; use 5 V-tolerant buffers when interfacing to higher-voltage buses.
Compliance Information
Legacy 5 V PLCC part produced before RoHS; uses tin-lead (SnPb) lead finish. Reach and conflict-mineral status not stated in manufacturer documentation. AEC-Q100 qualification not applicable for commercial-grade programmable logic in industrial/consumer use cases; military variants (EP1810GM883B) follow MIL-883B screening instead.
