EP1810LC-20T vs EP1810LC-30 Comparison
Detailed side-by-side comparison of EP1810LC-20T by Intel and EP1810LC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810LC-20T | EP1810LC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $9.95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 900 gates | — |
| Macrocells | 48 | 48 |
| Logic Array Blocks (LABs) | 4 x 12 macrocells | — |
| Maximum Toggle Frequency | 50 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | PLCC-68 (J-lead) | — |
| Mounting Type | Surface Mount (socket-compatible) | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial | — |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| Shipping Format | Tape & Reel ("T" suffix) | — |
| RoHS Status | Non-compliant (legacy 5V PLCC) | unknown (legacy ceramic package) |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Supply Voltage | — | 5 V (typical) |
| Technology | — | CMOS, low-power (LC) |
| Package | — | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Number of Pins | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |