EP1810LC-25 vs EP1810JI-35 Comparison

Detailed side-by-side comparison of EP1810LC-25 by Altera and EP1810JI-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810LC-25 EP1810JI-35
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.40 $18.60
Product Family Altera Classic EPLD —
Part Number EP1810LC-25 —
Macrocells 48 48
Propagation Delay (tPD) 25 ns —
Dedicated Inputs 12 48
I/O Pins 48 —
External Clock Inputs 4 —
Supply Voltage (VCC) 5 V (TTL-compatible) —
Operating Mode Turbo-only (no slow-power mode) —
Package 68-pin JLCC (J-leaded ceramic chip carrier) 28-pin JLCC (J-leaded ceramic, windowed)
Package Code LC = 68-pin JLCC —
Mounting Type Surface Mount Through-Hole (J-lead)
Technology CMOS EPLD (erasable programmable logic device) —
Programmable Interconnect Global + Local buses —
Programming Method Altera Classic programmer + MAX+PLUS II legacy flow —
Lifecycle Status Obsolete (legacy Altera Classic family) —
RoHS Status [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC]
Operating Temperature [DATA_NEEDED: temperature grade for LC package] -40C to +85C (Industrial)
Device Family — Classic EPLD
Logic Array Blocks — 8 LABs of 16 macrocells
Pin-to-Pin Propagation Delay (tPD) — 35 ns
Speed Grade — -35
Process Technology — CMOS EPROM (UV-erasable)
Supply Voltage — 5 V (typical classic EPLD)
Programmability — UV-erase, windowed for lab reprogram
MSL Level — [DATA_NEEDED: MSL rating]
Programming Interface — JEDEC fuse file via legacy programmer

Datasheets & Resources

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