EP1810LC-30 vs EP1810LC-20 Comparison
Detailed side-by-side comparison of EP1810LC-30 by Altera and EP1810LC-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810LC-30 | EP1810LC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $7.85 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 48 | 48 |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Supply Voltage | 5 V (typical) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, low-power (LC) | CMOS EPROM |
| Package | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 68-pin PLCC |
| Programming | Device programmer or JTAG | — |
| Operating Temperature | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Number of Pins | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| RoHS Status | unknown (legacy ceramic package) | [DATA_NEEDED: rohs status] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Maximum Operating Frequency | — | 50 MHz |
| Propagation Delay (tPD) | — | 20 ns |
| Programmability | — | UV-Erasable / OTP |
| Dedicated Inputs | — | 12 |
| Package Suffix | — | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | — | 20 ns (commercial) |
| Mounting Type | — | Surface Mount |