EP1810LC-30 vs EP1810LC-25T Comparison
Detailed side-by-side comparison of EP1810LC-30 by Altera and EP1810LC-25T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810LC-30 | EP1810LC-25T |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $8.40 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EP1810 |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Supply Voltage | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | CMOS, UV-erasable / OTP |
| Package | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Programming | Device programmer or JTAG | — |
| Operating Temperature | [DATA_NEEDED: temperature grade] | 0 °C to +70 °C (commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Number of Pins | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| RoHS Status | unknown (legacy ceramic package) | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Usable Gates | — | Approx. 900 |
| Dedicated Inputs | — | 16 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Supply Voltage (VCC) | — | 5 V nominal |
| Mounting Type | — | Surface Mount |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |