EP1810LC-25T - 48-Macrocell Classic EPLD, 25ns, PLCC-28 | Intel
MPN: EP1810LC-25T ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.95 | $129.50 |
| 100 | $11.2 | $1,120.00 |
| 500 | $9.75 | $4,875.00 |
| 1,000 | $8.4 | $8,400.00 |
Drop-in alternatives for EP1810LC-25T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1810LC-25
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →EP1810LC-20T
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP1810LC-20
✅ Drop-In✓ In Stock
$7.85 / Unit
View Datasheet →EP1810JC-25
✅ Drop-In✓ In Stock
$6.8 / Unit
View Datasheet →EP1810JC35
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EP1810LC-25T Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EP1810 |
| Device Type | EPLD (Erasable/OTP Complex PLD) |
| Macrocells | 48 (4 quadrants x 12 macrocells) |
| Usable Gates | Approx. 900 |
| Dedicated Inputs | 16 |
| Bidirectional I/O Pins | 48 |
| External Clocks | 4 |
| Propagation Delay (tPD) | 25 ns |
| Supply Voltage (VCC) | 5 V nominal |
| Operating Temperature | 0 °C to +70 °C (commercial) |
| Package | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Mounting Type | Surface Mount |
| Technology | CMOS, UV-erasable / OTP |
| I/O Standard | TTL-compatible 5 V |
| Programming Tool | Altera MAX+PLUS II / Quartus Classic |
EP1810LC-25T 28-pin j-lead plcc (plastic leaded chip carrier) Pin Configuration Guide
Complete pinout information for EP1810LC-25T (28-pin j-lead plcc (plastic leaded chip carrier) package) with 48 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1810LC-25T.
Refer to the datasheet for full pin configuration.
Estimated pin count: 48 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810LC-25T is suitable for 6 applications: 5V TTL Address Decoding, Peripheral Bus Glue Logic, State Machine Control Logic, Bus Arbitration & DMA Control, Industrial 5V Control Boards, Legacy Communication Interfaces.
5V TTL Address Decoding
The EP1810LC-25T is widely deployed as a 5 V TTL address decoder in legacy 8086, 8051, and Motorola 68k microprocessor systems where deterministic 25 ns tPD and non-volatile instant-on behavior are required. Its 48 macrocells easily absorb full 16-bit or 24-bit address-decode trees for memory and peripheral chip-select generation, replacing multiple 74LS138/74F139 decoder packages with a single device. The 5 V TTL-compatible I/O interfaces directly to the processor bus without level shifters, and the 28-pin PLCC footprint fits standard 5 V through-hole and SMT adapter boards used in industrial control cards.
Recommended
Peripheral Bus Glue Logic
The EP1810LC-25T excels as glue logic on PC/104, ISA, and STD peripheral buses where 5 V signalling, deterministic timing, and high I/O count are essential. Its 48 bidirectional I/O pins handle read/write strobe generation, interrupt acknowledgement, DMA arbitration, and chip-select multiplexing for multi-peripheral cards, while the 25 ns tPD comfortably meets the 8 MHz ISA bus timing budget. Designers use the EPLD's non-volatile configuration to ship production cards without separate boot PROMs, simplifying BOM and reducing board area on legacy industrial PCs.
Recommended
State Machine Control Logic
The 48 macrocells and deterministic timing of the EP1810LC-25T make it an ideal host for medium-complexity state machines controlling industrial stepper drives, scanner mechanisms, and legacy telecom line cards. Each macrocell provides a programmable flip-flop with sum-of-products logic, allowing multi-state Mealy or Moore machines to be implemented entirely in non-volatile silicon that powers up instantly into a known state. The 25 ns tPD plus 4 global clock networks enable synchronous designs up to roughly 20 MHz, sufficient for many motor-control and instrumentation loops.
Recommended
Bus Arbitration & DMA Control
Multi-master 5 V systems such as VMEbus, Multibus, and proprietary backplanes use the EP1810LC-25T to implement bus arbitration, DMA handshaking, and grant-chain logic in a single non-volatile device. The 16 dedicated inputs accommodate bus-request, bus-grant, and acknowledge lines from multiple masters, while the 48 I/O pins drive grant chains and DMA control signals. Deterministic 25 ns propagation is critical for arbitration latency in Multibus-II environments where multiple CPUs contend for the bus in tightly bounded cycles.
Recommended
Industrial 5V Control Boards
Factory-floor PLCs, CNC controllers, and process-instrumentation boards use the EP1810LC-25T to consolidate discrete 74LS glue logic, address decoding, and timing generation into one rugged 28-pin PLCC. The commercial 0 °C to 70 °C operating range covers most indoor cabinet environments, while the 5 V supply matches legacy analog front-ends and 5 V op-amps that dominate industrial analog I/O subsystems. The OTP/UV-erasable architecture provides field-upgradeable logic for low-volume industrial SKUs without requiring full FPGA toolchain expertise.
Recommended
Legacy Communication Interfaces
The EP1810LC-25T is used to implement glue logic for parallel-communication peripherals such as Centronics ports, IEEE-488 (GPIB) controllers, and SCSI-1 parallel interfaces that remain common in test-and-measurement equipment. Its 48 I/O pins implement handshake line generation, data-bus buffering control, and device-select decoding with deterministic timing, while the 5 V TTL interface matches legacy peripheral ICs without voltage translation. Designers benefit from consolidating up to a dozen discrete 74LS packages into a single instant-on device, simplifying EMI compliance on long parallel cables.
Recommended
Recommended Products Summary
Engineering reference data for EP1810LC-25T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810LC-25 | EP1810LC-20T | EP1810LC-20 | EP1810JC-25 | EP1810JC35 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | PLCC-28 (J-lead) | PLCC-28 (J-lead) - same | PLCC-28 (J-lead) - same | PLCC-28 (J-lead) - same | PLCC-28 (J-lead) - same | PLCC-28 (J-lead) - same |
| Propagation Delay (tPD) | 25 ns | 25 ns | 20 ns (-20%) | 20 ns (-20%) | 25 ns | 35 ns (+40%) |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 |
| Dedicated Inputs | 16 | 16 | 16 | 16 | 16 | 16 |
| Bidirectional I/O | 48 | 48 | 48 | 48 | 48 | 48 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C |
| Packaging Carrier | Tape & Reel | Tray/Tube | Tape & Reel | Tray/Tube | Tray/Tube | Tray/Tube |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Faster propagation delay than 35 ns alternative (vs EP1810JC35)
- Tape-and-reel carrier for SMT production (vs EP1810LC-25)
- Higher speed than 25 ns grade at marginal cost (vs EP1810JC-25)
Design Notes
Place a 100 nF ceramic decoupling capacitor as close as physically possible to each VCC pin of the EP1810LC-25T, plus a 10 µF tantalum or aluminum bulk capacitor within 25 mm of the device. The 5 V supply must remain within ±5 % tolerance during programming and operation; UV-erase retention and macrocell reliability depend on a stable rail. Estimated: at 5 V VCC with all 48 I/O pins switching CMOS loads at 10 MHz, expect roughly 150–250 mA peak supply current — design the regulator with at least 2× headroom for transient load steps.
Keep all I/O traces shorter than 50 mm when driving capacitive buses; if longer runs are unavoidable, add a 22–33 Ω series-damping resistor at the EPLD output to suppress transmission-line ringing on the 5 V TTL edges. The PLCC-28 socket footprint should be on a continuous ground pour on the inner layer to provide low-impedance return paths for the simultaneous-switching outputs (SSO). Estimated: SSO of 16 outputs at 25 ns edges can generate ~1 V of ground bounce if the ground pour is split.
Do not apply signals to the EP1810LC-25T I/O pins before VCC reaches 4.5 V — latch-up can occur because the device has 5 V-only CMOS I/O without 3.3 V tolerance. Use a power-good supervisor or RC delay to ensure input signals are released only after the EPLD rail is stable. Also note that OTP programming fuses cannot be reset in the PLCC package (no UV window); design iterations require a fresh device each time or a windowed LCC ceramic variant for laboratory use.
Compliance Information
RoHS and REACH status were not present in the verified web data and are marked as [DATA_NEEDED]; confirm with the manufacturer before use in Pb-free assemblies. The EP1810 series is a legacy Altera/Intel family and the 28-pin PLCC package historically used tin-lead (SnPb) lead finish on production parts.
