EP1810LC-30 vs EP1810LC-25T Comparación
Comparación detallada lado a lado de EP1810LC-30 por Altera y EP1810LC-25T por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LC-30 | EP1810LC-25T |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $8,40 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EP1810 |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Tensión de alimentación | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | CMOS, UV-erasable / OTP |
| Encapsulado | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Programming | Device programmer or JTAG | — |
| Temperatura de funcionamiento | [DATA_NEEDED: temperature grade] | 0 °C to +70 °C (commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Número de pines | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| Estado RoHS | unknown (legacy ceramic package) | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Usable Gates | — | Approx. 900 |
| Dedicated Inputs | — | 16 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Supply Voltage (VCC) | — | 5 V nominal |
| Tipo de montaje | — | Surface Mount |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |