EP1M350F780C7 vs EP1M350F780C6N Comparison
Detailed side-by-side comparison of EP1M350F780C7 by Intel and EP1M350F780C6N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP1M350F780C7
EP1M350F780C7 - Mercury FPGA 350K Gates 486 I/O BGA-780 | Intel
EP1M350F780C7 NrndIntel
EP1M350F780C6N
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N β Last Time BuySpecification Comparison
| Parameter | EP1M350F780C7 | EP1M350F780C6N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $162.00 | $219.40 |
| Family | Mercury (PLD) | Mercury (EP1M350) |
| Device Logic Elements | [DATA_NEEDED: exact LE count] | β |
| Logic Array Blocks (LABs) | 1440 | β |
| System Gates | 350,000 | 350,000 |
| Maximum User I/Os | 486 | β |
| Package | 780-ball FineLine BGA (F780) | 780-ball FC-FBGA (FINE LINE BGA-780) |
| Package Type | FINE LINE BGA-780 | β |
| Supply Voltage (Core) | 1.8 V | β |
| Logic Family | CMOS | CMOS, SRAM-based LUT |
| Operating Temperature | 0 C to 85 C (Commercial) | 0 C to 85 C |
| Mounting Type | Surface Mount | β |
| Transceivers / CDR Support | Up to 1.25 Gbps with CDR | β |
| Configuration Method | JTAG / Quartus II | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: rohs_status] |
| MSL Level | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: msl_level] |
| Process Technology | CMOS SRAM-based | β |
| Device Type | β | Loadable Programmable Logic Device (PLD) / FPGA |
| Logic Cells / Elements | β | 14,400 |
| User I/Os | β | 486 |
| Integrated Transceivers | β | Yes, with CDR up to 1.25 Gbps |
| Core Supply Voltage | β | 1.8 V |
| Terminal Form | β | Ball |
| Package Code (JEDEC) | β | S-PBGA-B780 |
| Configuration Interface | β | JTAG (IEEE 1149.1) / passive serial |
| Lead-Free | β | [DATA_NEEDED: lead_free] |
| Architecture | β | Look-up table (LUT)-based, optimized for high-speed serial I/O |
| Total Package Pins / Balls | β | 780 |