EP20K1000CF672C8ES vs EP20K1500CF33C8ES Comparison
Detailed side-by-side comparison of EP20K1000CF672C8ES by Intel and EP20K1500CF33C8ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K1000CF672C8ES - 1M-gate APEX20KE FPGA, 672-BGA | Intel
EP20K1000CF672C8ES β Last Time Buy
Specification Comparison
| Parameter | EP20K1000CF672C8ES | EP20K1500CF33C8ES |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $285.00 | $288.00 |
| Family | APEX 20K (APEX20KE) | β |
| Logic Elements | 38,400 | 51,840 |
| Typical Gates | 25,920 | β |
| Maximum System Gates | 1,000,000 | β |
| Embedded Memory (ESB) | 216 Kbits | β |
| User I/O Pins | 508 | β |
| Package | 672-ball FineLine BGA | 1020-FBGA (FCBGA), 33x33 mm |
| Speed Grade | C8 | -1 (C8) |
| Operating Temperature | Commercial (0C to +85C) | [DATA_NEEDED: operating temperature range] |
| Process Technology | 0.18 Β΅m CMOS | β |
| Core Voltage (VCCINT) | 2.5 V | β |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS, LVPECL, GTL, SSTL-2/3 | β |
| PLLs | 4 (ClockLock/ClockBoost) | β |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | ByteBlaster / MasterBlaster / Altera USB-Blaster |
| MSL Level | 3 (168 hours) | β |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance for ES variant] |
| Series | β | APEX 20K (APEX 20KE family) |
| Manufacturer | β | Intel (formerly Altera) |
| System Gates | β | 1,500,000 |
| Maximum Gates (Equivalent) | β | 2,392,000 |
| Embedded System Block (ESB) Bits | β | 442,368 |
| CAM Bits | β | 216 Kbit |
| Number of PLLs | β | 4 |
| Number of Clocks | β | 8 clock pins |
| Maximum User I/O | β | 808 (1020-FBGA) |
| Voltage - Supply (Core) | β | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) |
| I/O Standard Support | β | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) |
| JTAG / Boundary Scan | β | IEEE 1149.1 compliant |
| Sample Tier | β | ES (engineering sample) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |