EP20K1500CF33C8ES vs EP20K1500CF33C8 Comparison
Detailed side-by-side comparison of EP20K1500CF33C8ES by Intel and EP20K1500CF33C8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K1500CF33C8ES | EP20K1500CF33C8 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $288.00 | $1,090.00 |
| Series | APEX 20K (APEX 20KE family) | β |
| Manufacturer | Intel (formerly Altera) | β |
| System Gates | 1,500,000 | β |
| Maximum Gates (Equivalent) | 2,392,000 | β |
| Logic Elements | 51,840 | β |
| Embedded System Block (ESB) Bits | 442,368 | β |
| CAM Bits | 216 Kbit | β |
| Number of PLLs | 4 | 4 |
| Number of Clocks | 8 clock pins | β |
| Maximum User I/O | 808 (1020-FBGA) | β |
| Package | 1020-FBGA (FCBGA), 33x33 mm | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Speed Grade | -1 (C8) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 Β°C to +85 Β°C (Commercial) |
| Voltage - Supply (Core) | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) | β |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) | β |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | β |
| Programming Interface | ByteBlaster / MasterBlaster / Altera USB-Blaster | β |
| Sample Tier | ES (engineering sample) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance for ES variant] | Compliant per distributor listings |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes (per distributor specifications) |
| Family | β | APEX 20K |
| Logic Elements / Cells | β | 51,840 |
| Total RAM Bits | β | 442,368 |
| Number of Gates (typical) | β | 1,500,000 |
| Number of I/O | β | 808 (maximum user I/O) |
| Number of LABs/CLBs | β | 2,592 LABs (organized in MegaLABs) |
| Number of Embedded System Blocks | β | 216 ESBs |
| Supply Voltage (VCCINT) | β | 1.8 V (typical for APEX 20K core) |
| Supply Voltage (VCCIO) | β | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Package / Case | β | 1020-BBGA, FCBGA (FineLine BGA) |
| Number of Terminals | β | 1020 balls |
| Process Technology | β | 0.18 Β΅m CMOS, SRAM-based configuration |
| Configuration | β | SRAM-based, JTAG (IEEE 1149.1) |