EP20K1500CF33C8ES vs EP20K1500CF33C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K1500CF33C8ES sa pamamagitan ng Intel at EP20K1500CF33C8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K1500CF33C8ES | EP20K1500CF33C8 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | APEX 20K (APEX 20KE family) | — |
| Manufacturer | Intel (formerly Altera) | — |
| System Gates | 1,500,000 | — |
| Maximum Gates (Equivalent) | 2,392,000 | — |
| Logic Elements | 51,840 | — |
| Embedded System Block (ESB) Bits | 442,368 | — |
| CAM Bits | 216 Kbit | — |
| Number of PLLs | 4 | 4 |
| Number of Clocks | 8 clock pins | — |
| Maximum User I/O | 808 (1020-FBGA) | — |
| Packhaging | 1020-FBGA (FCBGA), 33x33 mm | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Speed Grade | -1 (C8) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (Commercial) |
| Voltage - Supply (Core) | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) | — |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Programming Interface | ByteBlaster / MasterBlaster / Altera USB-Blaster | — |
| Sample Tier | ES (engineering sample) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance for ES variant] | Compliant per distributor listings |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes (per distributor specifications) |
| Family | — | APEX 20K |
| Logic Elements / Cells | — | 51,840 |
| Total RAM Bits | — | 442,368 |
| Number of Gates (typical) | — | 1,500,000 |
| Number of I/O | — | 808 (maximum user I/O) |
| Number of LABs/CLBs | — | 2,592 LABs (organized in MegaLABs) |
| Number of Embedded System Blocks | — | 216 ESBs |
| Supply Voltage (VCCINT) | — | 1.8 V (typical for APEX 20K core) |
| Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Packhaging / Kaso | — | 1020-BBGA, FCBGA (FineLine BGA) |
| Number of Terminals | — | 1020 balls |
| Process Technology | — | 0.18 µm CMOS, SRAM-based configuration |
| Configuration | — | SRAM-based, JTAG (IEEE 1149.1) |