EP20K1500CF33C8ES vs EP20K1500CF33C8 Comparaison
Comparaison détaillée côte à côte de EP20K1500CF33C8ES par Intel et EP20K1500CF33C8 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K1500CF33C8ES | EP20K1500CF33C8 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $288,00 | $1 090,00 |
| Series | APEX 20K (APEX 20KE family) | — |
| Manufacturer | Intel (formerly Altera) | — |
| System Gates | 1,500,000 | — |
| Maximum Gates (Equivalent) | 2,392,000 | — |
| Logic Elements | 51,840 | — |
| Embedded System Block (ESB) Bits | 442,368 | — |
| CAM Bits | 216 Kbit | — |
| Number of PLLs | 4 | 4 |
| Number of Clocks | 8 clock pins | — |
| Maximum User I/O | 808 (1020-FBGA) | — |
| Boîtier | 1020-FBGA (FCBGA), 33x33 mm | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Speed Grade | -1 (C8) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (Commercial) |
| Voltage - Supply (Core) | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) | — |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Programming Interface | ByteBlaster / MasterBlaster / Altera USB-Blaster | — |
| Sample Tier | ES (engineering sample) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance for ES variant] | Compliant per distributor listings |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes (per distributor specifications) |
| Family | — | APEX 20K |
| Logic Elements / Cells | — | 51,840 |
| Total RAM Bits | — | 442,368 |
| Number of Gates (typical) | — | 1,500,000 |
| Number of I/O | — | 808 (maximum user I/O) |
| Number of LABs/CLBs | — | 2,592 LABs (organized in MegaLABs) |
| Number of Embedded System Blocks | — | 216 ESBs |
| Supply Voltage (VCCINT) | — | 1.8 V (typical for APEX 20K core) |
| Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Boîtier / Format | — | 1020-BBGA, FCBGA (FineLine BGA) |
| Number of Terminals | — | 1020 balls |
| Process Technology | — | 0.18 µm CMOS, SRAM-based configuration |
| Configuration | — | SRAM-based, JTAG (IEEE 1149.1) |