EP20K200CF484C7N vs EP20K200CF484C9N Comparison

Detailed side-by-side comparison of EP20K200CF484C7N by Altera and EP20K200CF484C9N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K200CF484C7N

EP20K200CF484C7N - APEX-20K 200K Gates FPGA 484-FBGA | Intel/Altera

EP20K200CF484C7N Obsolete
Altera
EP20K200CF484C9N

EP20K200CF484C9N - 200K Gate APEX 20KC FPGA | Altera | BGA-484

EP20K200CF484C9N Obsolete

Specification Comparison

Parameter EP20K200CF484C7N EP20K200CF484C9N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $62.00 $201.04
Series APEX-20K β€”
Logic Elements / Cells 8,320 β€”
Total RAM Bits 106,496 β€”
Number of Gates (typical) 200,000 β€”
Number of I/O 382 β€”
Voltage - Supply (VCCINT) 1.71 V to 1.89 V β€”
Package / Case 484-BBGA (FineLine BGA) β€”
Supplier Device Package 484-FBGA (23x23 mm) β€”
Mounting Type Surface Mount Surface Mount (BGA)
Operating Temperature 0C to +85C (commercial grade) β€”
Number of PLLs 4 β€”
Embedded Array Blocks (EABs) Configurable as RAM/ROM/FIFO β€”
Programmable Logic Blocks APEX LAB architecture β€”
MultiVolt I/O Support 1.8V / 2.5V / 3.3V / 5V β€”
Configuration Method SRAM-based, in-system reconfigurable β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] Compliant
Lifecycle Status Obsolete (Altera/Intel APEX-20K family EOL) β€”
Family β€” APEX 20KC
Device Type β€” FPGA (Field-Programmable Gate Array)
Typical Gates β€” 200,000
Logic Elements β€” 8,320
Embedded System Block (ESB) Bits β€” 106,496
Maximum User I/O β€” 376
Maximum Clock Frequency β€” 250 MHz
Process Technology β€” 0.15 um CMOS
Core Supply Voltage (VCCINT) β€” 1.8 V
I/O Supply Voltage (VCCIO) β€” 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt)
Package β€” 484-pin FineLine BGA (FBGA)
Speed Grade β€” C9 (250 MHz)
Temperature Grade β€” Industrial (0C to +85C)
Configuration Scheme β€” SRAM-based, supports passive serial/parallel and JTAG
MSL Level β€” 3 (per JEDEC J-STD-020)

Datasheets & Resources

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