EP20K200CF484C7N vs EP20K200CF484C9N Perbandingan
Perbandingan bersamaan detil EP20K200CF484C7N dari Altera dan EP20K200CF484C9N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EP20K200CF484C7N - APEX-20K 200K Gates FPGA 484-FBGA | Intel/Altera
EP20K200CF484C7N Obsolete
Perbandingan Spesifikasi
| Parameter Umum | EP20K200CF484C7N | EP20K200CF484C9N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Series | APEX-20K | — |
| Logic Elements / Cells | 8,320 | — |
| Total RAM Bits | 106,496 | — |
| Number of Gates (typical) | 200,000 | — |
| Number of I/O | 382 | — |
| Voltage - Supply (VCCINT) | 1.71 V to 1.89 V | — |
| Paket / Case | 484-BBGA (FineLine BGA) | — |
| Supplier Device Package | 484-FBGA (23x23 mm) | — |
| Tipe Mounting | Surface Mount | Surface Mount (BGA) |
| Suhu Kerja | 0C to +85C (commercial grade) | — |
| Number of PLLs | 4 | — |
| Embedded Array Blocks (EABs) | Configurable as RAM/ROM/FIFO | — |
| Programmable Logic Blocks | APEX LAB architecture | — |
| MultiVolt I/O Support | 1.8V / 2.5V / 3.3V / 5V | — |
| Configuration Method | SRAM-based, in-system reconfigurable | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Status Lingkungan Hidup | Obsolete (Altera/Intel APEX-20K family EOL) | — |
| Family | — | APEX 20KC |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Typical Gates | — | 200,000 |
| Logic Elements | — | 8,320 |
| Embedded System Block (ESB) Bits | — | 106,496 |
| Maximum User I/O | — | 376 |
| Frekuensi Bawah Maximum | — | 250 MHz |
| Process Technology | — | 0.15 um CMOS |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) |
| Paket | — | 484-pin FineLine BGA (FBGA) |
| Speed Grade | — | C9 (250 MHz) |
| Temperature Grade | — | Industrial (0C to +85C) |
| Configuration Scheme | — | SRAM-based, supports passive serial/parallel and JTAG |
| Level MSL | — | 3 (per JEDEC J-STD-020) |