EP20K200CF484I7 vs EP20K200FC484-1 Comparison
Detailed side-by-side comparison of EP20K200CF484I7 by Altera and EP20K200FC484-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K200CF484I7 - APEX 20KC 200K Gates FPGA 1.8V FBGA-484 | Altera
EP20K200CF484I7 β Last Time BuySpecification Comparison
| Parameter | EP20K200CF484I7 | EP20K200FC484-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $89.50 | $119.00 |
| Family | APEX 20KC | APEX 20K |
| Logic Elements | 8,320 | β |
| Typical Gate Count | 200,000 system gates | β |
| Maximum Operating Frequency | 375.94 MHz (per device-family data) | 250 MHz |
| Process Technology | 0.15 Β΅m CMOS with copper interconnect | 0.22 Β΅m CMOS |
| Internal Supply Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | β |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | β |
| User I/O Pins | 376 | β |
| Dedicated Inputs | 4 | β |
| Package | 484-pin FBGA (FineLine BGA) | 484-ball FBGA (FineLine BGA) |
| Package Body Size | 23 mm Γ 23 mm | β |
| Ball Pitch | 1.000 mm | β |
| Speed Grade | -7 | -1 (fastest bin) |
| Temperature Grade (I7 suffix) | Industrial, -40 Β°C to +85 Β°C | β |
| Configuration Technology | SRAM-based, re-programmable in-system | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Propagation Delay | [DATA_NEEDED: datasheet-specified tpd] | 2.5 ns |
| Logic Elements / Cells | β | 8320 |
| System Gates | β | 200 K |
| Embedded Memory (RAM bits) | β | 106,496 bits |
| Number of I/Os | β | 382 |
| Number of LABs/CLBs | β | [DATA_NEEDED: LAB count] |
| Core Supply Voltage | β | 2.5 V |
| Operating Temperature | β | 0 Β°C to 85 Β°C (Commercial) |
| Mounting Type | β | Surface Mount |
| Architecture | β | MultiCore (LUT + Embedded System Blocks) |
| Programming Interface | β | IEEE 1149.1 JTAG |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |