EP20K200CF484I7 vs EP20K200FC484-1 Vergleich
Detaillierter Direktvergleich von EP20K200CF484I7 von Altera und EP20K200FC484-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K200CF484I7 - APEX 20KC 200K Gates FPGA 1.8V FBGA-484 | Altera
EP20K200CF484I7 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP20K200CF484I7 | EP20K200FC484-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $89,50 | $119,00 |
| Family | APEX 20KC | APEX 20K |
| Logic Elements | 8,320 | — |
| Typical Gate Count | 200,000 system gates | — |
| Maximum Operating Frequency | 375.94 MHz (per device-family data) | 250 MHz |
| Process Technology | 0.15 µm CMOS with copper interconnect | 0.22 µm CMOS |
| Internal Supply Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| User I/O Pins | 376 | — |
| Dedicated Inputs | 4 | — |
| Gehäuse | 484-pin FBGA (FineLine BGA) | 484-ball FBGA (FineLine BGA) |
| Package Body Size | 23 mm × 23 mm | — |
| Ball Pitch | 1.000 mm | — |
| Speed Grade | -7 | -1 (fastest bin) |
| Temperature Grade (I7 suffix) | Industrial, -40 °C to +85 °C | — |
| Configuration Technology | SRAM-based, re-programmable in-system | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Propagation Delay | [DATA_NEEDED: datasheet-specified tpd] | 2.5 ns |
| Logic Elements / Cells | — | 8320 |
| System Gates | — | 200 K |
| Embedded Memory (RAM bits) | — | 106,496 bits |
| Number of I/Os | — | 382 |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Core Supply Voltage | — | 2.5 V |
| Betriebstemperatur | — | 0 °C to 85 °C (Commercial) |
| Montageart | — | Surface Mount |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Programming Interface | — | IEEE 1149.1 JTAG |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |