EP20K200EBC652-3 vs EP20K200EBC652-3N Comparison

Detailed side-by-side comparison of EP20K200EBC652-3 by Intel and EP20K200EBC652-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K200EBC652-3 EP20K200EBC652-3N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family APEX-20KE —
Logic Elements (LEs) 8,320 —
Logic Array Blocks (LABs) 832 832
Total RAM Bits 106,496 —
Maximum User I/O Pins 376 —
Embedded System Blocks (ESBs) Yes (dual-port RAM / ROM / CAM) —
PLLs 4 —
Package 652-ball FineLine BGA (top-side, 1.27 mm pitch) 652-ball BGA
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +85C (EBC - Enhanced Commercial) —
Speed Grade -3 -3 (slowest in APEX 20KE family)
Configuration Mode JTAG / PS / Passive-serial / Passive-parallel —
Process Node [DATA_NEEDED: process node] —
Core Voltage [DATA_NEEDED: core voltage] —
RoHS Status Not RoHS (non-lead-free variant) Compliant
Lifecycle Status Obsolete - last time-buy period closed —
Series — APEX 20KE (APEX-20KE®)
Device Family — EP20K200
System Gates — 200,000
Logic Elements / Cells — 8,320
Macrocells — 832
Embedded RAM — 106,496 bits
User I/Os (DigiKey listing) — 376
User I/Os (digchip listing) — 277
Propagation Delay — 2.33 ns
Internal Frequency (max) — 189 MHz
Process Technology — 0.22 µm CMOS
Core Supply Voltage — 1.71 V to 1.89 V (nominal 1.8 V)
I/O Supply (LVDS-capable) — LVDS, 2.5 V referenced (per source variant)
Operating Temperature (TJ) — 0 °C to 85 °C (commercial)
Configuration — JTAG (IEEE 1149.1), Passive Serial

Datasheets & Resources

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